参数资料
型号: AT93C46B-10SC-2.5
厂商: Atmel Corp.
英文描述: 3-Wire Serial E2PROMs
中文描述: 3线串行E2PROMs
文件页数: 6/10页
文件大小: 143K
代理商: AT93C46B-10SC-2.5
AT93C46B
6
Functional Description
The AT93C46B is accessed via a simple and versatile
three-wire serial communication interface. Device opera-
tion is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS
and consists of a Start Bit (logic ‘1’) followed by the appro-
priate Op Code and the desired memory Address location.
READ (READ):
The Read (READ) instruction contains
the Address code for the memory location to be read. After
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the ris-
ing edges of serial clock SK. It should be noted that a
dummy bit (logic ‘0’) precedes the 16 bit data output string.
ERASE/WRITE (EWEN):
To assure data integrity, the
part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, program-
ming remains enabled until an Erase/Write Disable
(EWDS) instruction is executed or V
CC
power is removed
from the part.
ERASE (ERASE):
The Erase (ERASE) instruction pro-
grams all bits in the specified memory location to the logical
‘1’ state. The self-timed erase cycle starts once the ERASE
instruction and address are decoded. The DO pin outputs
the READY / BUSY status of the part if CS is brought high
after being kept low for a minimum of 250 ns (t
CS
). A logic
‘1’ at pin DO indicates that the selected memory location
has been erased, and the part is ready for another instruc-
tion.
WRITE (WRITE):
the 16 bits of data to be written into the specified memory
location. The self-timed programming cycle starts after the
last bit of data is received at serial data input pin DI. The
DO pin outputs the READY/BUSY status of the part if CS is
brought high after being kept low for a minimum of 250 ns
(t
CS
). A logic ‘0’ at DO indicates that programming is still in
progress. A logic ‘1’ indicates that the memory location at
the specified address has been written with the data pat-
tern contained in the instruction and the part is ready for
further instructions.
ERASE ALL (ERAL):
The Erase All (ERAL) instruction
programs every bit in the memory array to the logic ‘1’ state
and is primarily used for testing purposes. The DO pin out-
puts the READY/BUSY status of the part if CS is brought
high after being kept low for a minimum of 250 ns (t
CS
). The
ERAL instruction is valid only at V
CC
= 5.0V
±
10%.
WRITE ALL (WRAL):
The Write All (WRAL) instruction
programs all memory locations with the data patterns spec-
ified in the instruction. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after
being kept low for a minimum of 250 ns (t
CS
). The WRAL
instruction is valid only at V
CC
= 5.0V
±
10%.
ERASE/WRITE DISABLE (EWDS):
accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.
The Write (WRITE) instruction contains
To protect against
Synchronous Data Timing
Note:
1.
This is the minimum SK period.
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