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| 型号： | ATF1500ABV-15JC |
| 厂商： | Atmel |
| 文件页数： | 4/18页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 32 MACROCELL LV 44PLCC |
| 标准包装： | 27 |
| 系列： | ATF15xx |
| 可编程类型： | 系统内可编程（最少 10,000 次编程/擦除循环） |
| 最大延迟时间 tpd(1)： | 15.0ns |
| 电压电源 - 内部： | 3 V ~ 5.25 V |
| 宏单元数： | 32 |
| 输入/输出数： | 32 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 管件 |
12
0723K–PLD–6/05
ATF1500ABV
22. Power-up Reset
The ATF1500ABV’s registers are designed to reset during power-up. At a point delayed slightly
from V
CC crossing VRST, all registers will be reset to the low state. As a result, the registered out-
put state will always be low on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
CC actually rises in the system, the following conditions are
required:
1.
The V
CC rise must be monotonic.
2.
Signals from which clocks are derived must remain stable during T
PR.
3.
After T
PR occurs, all input and feedback setup times must be met before driving the
clock signal high.
23. Power-down Mode
The ATF1500ABV includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur-
rent is reduced to less than 10 A. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a High-Z state at the onset of power-down will remain at High-Z. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches
remain active to ensure that pins do not float to indeterminate levels, further reducing system
power. The power-down pin feature is enabled in the logic design file. Designs using the power-
down pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
24. Register Preload
The ATF1500ABV’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the reg-
isters to control test sequencing. A JEDEC file with preload is generated when a source file with
preload vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done
automatically when vectors are run by any approved programmers. The preload mode is
enabled by raising an input pin to a high voltage level. Contact Atmel PLD Applications for PRE-
LOAD pin assignments, timing and voltage requirements.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ATF1500ABV-15JI | 功能描述:IC CPLD 15NS LOW VOLT PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:ATF15xx 标准包装:40 系列:ispMACH® 4000C 可编程类型:系统内可编程 最大延迟时间 tpd(1):5.0ns 电压电源 - 内部:1.65 V ~ 1.95 V 逻辑元件/逻辑块数目:32 宏单元数:512 门数:- 输入/输出数:128 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:176-LQFP 供应商设备封装:176-TQFP（24x24） 包装:托盘 |
| ATF1500ABVL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF1500ABVL-25AC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF1500ABVL-25JC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF1500AL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High Performance E2 PLD |
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