参数资料
型号: ATF1500AL-20JC
厂商: Atmel
文件页数: 1/19页
文件大小: 0K
描述: IC CPLD 20NS 44PLCC
标准包装: 27
系列: ATF15xx
可编程类型: 系统内可编程(最少 100 次编程/擦除循环)
最大延迟时间 tpd(1): 20.0ns
电压电源 - 内部: 4.75 V ~ 5.25 V
宏单元数: 32
输入/输出数: 32
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC
包装: 管件
其它名称: ATF1500AL20JC
1
TQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
I/O
GND
I/O
VCC
I/O
VCC
I/O
GND
I/O
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
I/O
GND
VCC
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
PLCC
Top View
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
I/O
GND
I/O
VCC
I/O
VCC
I/O
GND
I/O
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
I/O
GND
VCC
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
Pin Configurations
Pin
Name
Function
CLK
Clock
I
Logic Inputs
I/O
Bi-directional
Buffers
GCLR
Register Reset
(active low)
OE1,
OE2
Output Enable
(active low)
VCC
+5V Supply
PD
Power-down
(active high)
Features
High-density, High-performance Electrically-erasable Complex
Programmable Logic Device
– 44-pin, 32 I/O CPLD
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation Up to 125 MHz
– Fully Connected Input and Feedback Logic Array
– Backward Compatibility with ATF1500/L Software and Hardware
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
Advanced Power Management Features
– Automatic 3 mA Standby (ATF1500AL)
– Pin-controlled 10 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and TQFP Packages
Advanced Flash Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
Supported by Popular third-arty Tools
Security Fuse Feature
Pin-compatible with the Most Commonly Used Devices
Green (Pb/Halide-fee/RoHS Compliant) Package Options
Description
The ATF1500A is a high-performance, high-density complex PLD. Built on an
advanced Flash technology, it has maximum pin-to-pin delays of 7.5 ns and supports
sequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and up
to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs.
The ATF1500A’s global input and feedback architecture simplifies logic placement
and eliminates pinout changes due to design changes.
High-
performance
EPLD
ATF1500A
ATF1500AL
Rev. 0759F–6/05
(continued)
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