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参数资料
| 型号： | ATF1508ASL-20AC100 |
| 厂商： | Atmel |
| 文件页数： | 27/31页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128 MACROCELL LP 100TQFP |
| 标准包装： | 90 |
| 系列： | ATF15xx |
| 可编程类型： | 系统内可编程（最少 10,000 次编程/擦除循环） |
| 最大延迟时间 tpd(1)： | 20.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 宏单元数： | 128 |
| 输入/输出数： | 80 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 608 (CN2011-ZH PDF) |
| 配用： | ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S |
| 其它名称： | ATF1508ASL20AC100 |
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5
ATF1508AS(L)
0784P–PLD–7/05
Flip-flop
The ATF1508AS’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.
The clock itself can be either the Global CLK Signal (GCK) or an individual product term. The
flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock,
one of the macrocell product terms can be selected as a clock enable. When the clock enable
function is active and the enable signal (product term) is low, all clock edges are ignored. The
flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-
nous preset (AP) can be a product term or always off.
Extra Feedback
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or a registered signal regardless of
whether the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-
ation of a second latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-
vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
Global Bus/Switch
Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to
the logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus
and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The 16 foldback terms in each region allows generation of high fan-in sum
terms (up to 21 product terms) with a little additional delay.
3.3V or 5.0V I/O
Operation
The ATF1508AS device has two sets of V
CC pins viz, VCCINT and VCCIO. VCCINT pins must
always be connected to a 5.0V power supply. V
CCINT pins are for input buffers and are “com-
patible” with both 3.3V and 5.0V inputs. V
CCIO pins are for I/O output drives and can be
connected for 3.3/5.0V power supply.
Open-collector
Output Option
This option enables the device output to provide control signals such as an interrupt that can
be asserted by any of the several devices.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ATF1508ASL-20JC84 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD 128 MACROCELL w/ISP LOW PWR 5V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF1508ASL-20QC100 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD 128 MACROCELL w/ISP LOW PWR 5V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF1508ASL-20QC160 | 功能描述:CPLD - 复杂可编程逻辑器件 128 MACROCELL w/ISP LO-PWR 5V-20NS RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF1508ASL-25AI100 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD 128 MACROCELL 5V 25NS IND TEMP RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF1508ASL-25AI160 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
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