参数资料
| 型号： | ATF20V8B-15SC |
| 厂商： | Atmel |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | IC PLD EE 15NS 24-SOIC |
| 标准包装： | 31 |
| 系列： | 20V8 |
| 可编程类型： | EE PLD |
| 宏单元数： | 8 |
| 输入电压： | 5V |
| 速度： | 15ns |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 管件 |
| 其它名称： | ATF20V8B15SC |
ATF20V8B(Q)(L)
5
Input Test Waveforms and
Measurement Levels
t
R, tF < 5 ns (10% to 90%)
Output Test Loads
Commercial
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power-up. At a point delayed slightly from V
CC crossing
V
RST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the fol-
lowing conditions are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3.
The clock must remain stable during t
PR.
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
Pin Capacitance
f = 1 MHz, T = 25°C
Typ
Max
Units
Conditions
CIN
58
pF
VIN = 0V
C
OUT
68
pF
V
OUT = 0V
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1,000
ns
V
RST
Power-up Reset Voltage
3.8
4.5
V
相关PDF资料 |
PDF描述 |
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| ATF20V8B-15PI | IC PLD 15NS 24DIP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ATF20V8B-15SI | 功能描述:SPLD - 简单可编程逻辑器件 300 GATE EPLD 15NS IND TEMP RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| ATF20V8B-15XC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF20V8B-15XI | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF20V8B-25GC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable PLD |
| ATF20V8B-25GI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable PLD |
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