参数资料
| 型号： | ATF20V8BQL-15SI |
| 厂商： | Atmel |
| 文件页数： | 19/22页 |
| 文件大小： | 0K |
| 描述： | IC PLD EE 15NS "QZ" PWR 24-SOIC |
| 标准包装： | 31 |
| 系列： | 20V8 |
| 可编程类型： | EE PLD |
| 宏单元数： | 8 |
| 输入电压： | 5V |
| 速度： | 15ns |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 管件 |
| 其它名称： | ATF20V8BQL15SI |
ATF20V8B(Q)(L)
6
Input and I/O Pull-ups
All ATF20V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to V
CC.
This
ensures that all logic array inputs are at known states.
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).
Input Diagram
I/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the
ATF20V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.
The ATF20V8B can be configured in one of three different
modes. Each mode makes the ATF20V8B look like a dif-
ferent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter-
mining factors would be the usage of register versus com-
binatorial outputs and dedicated outputs versus outputs
with output enable control.
The ATF20V8B universal architecture can be programmed
to emulate many 24-pin PAL devices. These architectural
subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF20V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the content of the ATF20V8B.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessi-
ble regardless of the state of the security fuse.
相关PDF资料 |
PDF描述 |
|---|---|
| ATF20V8B-15PC | IC PLD 15NS 24DIP |
| ATF16V8C-7JU | IC PLD 7NS 20PLCC |
| ABB75DHAS | CONN EDGECARD 150PS R/A .050 SLD |
| ATF22V10CZ-12SC | IC PLD 12NS 24SOIC |
| AMM40DRMN | CONN EDGECARD 80POS .156 WW |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ATF20V8BQL-15XC | 功能描述:SPLD - 简单可编程逻辑器件 300 GATE QUARTER/ LOW POWER 5V - 15NS RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| ATF20V8BQL-15XI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable PLD |
| ATF20V8BQL-25JC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF20V8BQL-25JI | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF20V8BQL-25PC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:High- Performance EE PLD |
发布紧急采购，3分钟左右您将得到回复。