参数资料
| 型号： | ATF22LV10C-10SC |
| 厂商： | Atmel |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC PLD EE 10NS 24-SOIC |
| 标准包装： | 31 |
| 系列： | 22V10 |
| 可编程类型： | EE PLD |
| 宏单元数： | 10 |
| 输入电压： | 3.3V |
| 速度： | 10ns |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 管件 |
7
0780M–PLD–7/10
Atmel ATF22LV10C
8.
Power-down Mode
The Atmel ATF22LV10C includes an optional pin controlled power-down feature. When this mode is enabled, the
PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the
PD pin is high, the device supply current is reduced to less than 100mA. During power-down, all output data and
internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs which were in an undetermined state at the onset of power-down will remain at the same state. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
insure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is
enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input.
However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When
the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input.
Note:
Some programmers list the 22V10 JEDEC-compatible 22V10C (no PD used) separately from the non-22V10 JEDEC-
compatible 22V10CEX (with PD used).
Figure 8-1.
Input Diagram
Figure 8-2.
I/O Diagram
ESD
PROTECTION
CIRCUIT
VCC
INPUT
100K
VCC
100K
INPUT
OE
DATA
VCC
I/O
相关PDF资料 |
PDF描述 |
|---|---|
| IDT71321LA25J8 | IC SRAM 16KBIT 25NS 52PLCC |
| IDT71321LA35TF8 | IC SRAM 16KBIT 35NS 64STQFP |
| IDT71V321L55PF | IC SRAM 16KBIT 55NS 64TQFP |
| ATF22LV10C-10PC | IC PLD 10CELL 3V 10NS 24DIP |
| IDT71V321L55TF | IC SRAM 16KBIT 55NS 64STQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ATF22LV10C-10SI | 功能描述:SPLD - 简单可编程逻辑器件 EEPLD 500GATE STDPWR 3.3V 10NS IND TEMP RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| ATF22LV10C-10SU | 功能描述:SPLD - 简单可编程逻辑器件 500 GATE STANDARD POWER 3.3V - 10NS RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| ATF22LV10C-10XC | 功能描述:SPLD - 简单可编程逻辑器件 EEPLD 500GATE STDPWR 3.3V 10NS IND TEMP RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| ATF22LV10C-10XI | 功能描述:SPLD - 简单可编程逻辑器件 ASICS RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| ATF22LV10C-10XU | 功能描述:SPLD - 简单可编程逻辑器件 EEPLD 500GATE STDPWR 3.3V 10NS IND TEMP RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
发布紧急采购，3分钟左右您将得到回复。