参数资料
型号: ATF22V10CZ-12XC
厂商: Atmel
文件页数: 15/19页
文件大小: 0K
描述: IC PLD 12NS 24TSSOP
标准包装: 5,000
系列: 22V10
可编程类型: EE PLD
宏单元数: 10
输入电压: 5V
速度: 12ns
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
其它名称: ATF22V10CZ12XC
5
0778L–PLD–8/10
Atmel ATF22V10C(Q)Z
4.4
Input Test Waveforms
4.4.1
Input Test Waveforms and Measurement Levels
4.4.2
Output Test Loads
Note:
Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’
delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification
conditions.
4.5
Pin Capacitance
Table 4-1.
Pin Capacitance (f = 1MHz,T=25C(1)
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
4.6
Power-up Reset
The registers in the Atmel ATF22V10CZ/CQZ are designed to reset during power-up. At a point delayed slightly
from V
CC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the following conditions are required:
1.
The V
CC rise must be monotonic and start below 0.7V
2.
The clock must remain stable during T
PR
3.
After T
PR occurs, all input and feedback setup times must be met before driving the clock pin high
4.7
Preload of Register Outputs
The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
Typ
Max
Units
Conditions
C
IN
810
pF
V
IN = 0V; f = 1.0MHz
C
I/O
810
pF
V
OUT = 0V; f = 1.0MHz
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