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参数资料
| 型号： | ATF2500C-20JC |
| 厂商： | Atmel |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC CPLD EE 20NS 44PLCC |
| 标准包装： | 27 |
| 系列： | ATF2500C(L) |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 20.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 宏单元数： | 24 |
| 输入/输出数： | 24 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 管件 |
| 产品目录页面： | 608 (CN2011-ZH PDF) |
3
0777K–PLD–1/24/08
ATF2500C
3.
Using the ATF2500C Family’s Many Advanced Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
Fully Connected Logic Array – Each array input is always available to every product term.
This makes logic placement a breeze.
Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also
easily created. These options allow more efficient product term usage.
Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to feed
its input (D/T2) directly back to the logic array. This provides further logic expansion capability
without using precious pin resources.
Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops has
a dedicated clock product term. This removes the constraint that all registers use the same
clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing
higher performance pin clocking and flexible product term clocking within one design.
A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48.
Each register has its own clock and reset terms, as well as its own sum term.
Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a dedicated
input path. Each of the 48 registers has its own feedback term into the array as well. These
features, combined with individual product terms for each I/O’s output enable, facilitate true
bi-directional I/O design.
Combinable Sum Terms – Each output macrocell’s three sum terms may be combined into
a single term. This provides a fan in of up to 12 product terms per sum term with no speed
penalty.
Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.
User Row (64 bits) – Use to store information such as unit history.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ATF2500C-20JI | 功能描述:CPLD - 复杂可编程逻辑器件 2500 GATE 24 MACRO STD PWR 5V-20NS RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF2500C-20KM | 功能描述:CPLD - 复杂可编程逻辑器件 STD PWR 2500 GATE 24 MACROCELL 5V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF2500C-20LM | 功能描述:CPLD - 复杂可编程逻辑器件 ASICS RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF2500C-20PC | 功能描述:CPLD - 复杂可编程逻辑器件 2500 GATE 24 MACRO STD PWR 5V-20NS RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ATF2500C-20PI | 功能描述:CPLD - 复杂可编程逻辑器件 2500 GATE 24 MACRO STD PWR 5V-20NS RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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