参数资料
型号: ATF2500C-20PI
厂商: Atmel
文件页数: 19/24页
文件大小: 0K
描述: IC CPLD EE 20NS 40DIP
标准包装: 10
系列: ATF2500C(L)
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 20.0ns
电压电源 - 内部: 4.5 V ~ 5.5 V
宏单元数: 24
输入/输出数: 24
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 40-DIP(0.600",15.24mm)
供应商设备封装: 40-PDIP
包装: 管件
4
0777K–PLD–1/24/08
ATF2500C
4.
Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from V
CC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how V
CC actually rises in
the system, the following conditions are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3.
The clock pin, and any signals from which clock terms are derived, must remain stable
during t
PR.
Figure 4-1.
Power-up Reset Waveform
Table 4-1.
Power-up Reset
Parameter
Description
Typ
Max
Units
t
PR
Power-up Reset Time
600
1000
ns
V
RST
Power-up Reset Voltage
3.8
4.5
V
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