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参数资料
型号： ATMEGA329V-8MUR
厂商： Atmel
文件页数： 13/146页
文件大小： 0K
描述： MCU AVR 32K FLASH 8MHZ 64QFN
产品培训模块： megaAVR Introduction
标准包装： 4,000
系列： AVR® ATmega
核心处理器： AVR
芯体尺寸： 8-位
速度： 8MHz
连通性： SPI，UART/USART，USI
外围设备： 欠压检测/复位，LCD，POR，PWM，WDT
输入/输出数： 54
程序存储器容量： 32KB（16K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
数据转换器： A/D 8x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 64-VFQFN 裸露焊盘
包装： 带卷 (TR)
其它名称： ATMEGA329V-8MUR-ND
ATMEGA329V-8MURTR
20
2552K–AVR–04/11
ATmega329/3290/649/6490
Figure 7-3.
On-chip Data SRAM Access Cycles
7.3
EEPROM Data Memory
The ATmega329/3290/649/6490 contains 1/2K bytes of data EEPROM memory. It is organized
as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page 308, page 313, and page 296 respectively.
7.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 7-1. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
CC is likely to rise or fall slowly on power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page 21. for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
7.3.2
EEPROM Write During Power-down Sleep Mode
When entering Power-down sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the Write Access time has
passed. However, when the write operation is completed, the clock continues running, and as a
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
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