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参数资料
| 型号： | ATR4256-TKSY |
| 厂商： | Atmel |
| 文件页数： | 12/21页 |
| 文件大小： | 0K |
| 描述： | IC FREQ SYNTH RADIO TUNER 20SSOP |
| 产品变化通告： | ATR425x Obsolescence 03/Apr/2012 |
| 标准包装： | 830 |
| 功能： | 频率合成器 |
| RF 型： | 广播无线电 |
| 次要属性： | 缓冲输出 |
| 封装/外壳： | 20-SOIC（0.209"，5.30mm 宽） |
| 包装： | 管件 |
5. Application Information
Figure 5-1.
FMOSCIN Sensitivity
Vi (mV rms on 50 ? )
150
100
50
0
0
20
40
60
80
100
120
140
160
Frequency (MHz)
6. 3-wire Bus Description
The register settings of ATR4256 are programmed by a 3-wire bus protocol. The bus protocol
consists of separate commands. A defined number of bits are transmitted sequentially during
each command.
One command is used to program all the bits of one register. The different registers available
(see “Data Transfer” on page 14 ) are addressed by the length of the command (number of trans-
mitted bits) and by two address bits, that are unique to each register of a given length. 16-bit
registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit
commands.
Each bus command starts with a rising edge on the enable line (EN) and ends with a falling edge
on EN. EN has to be kept HIGH during the bus command.
The sequence of transmitted bits during one command starts with the LSB of the first byte and
ends with the MSB of the last byte of the register addressed. To transmit one bit (0 or 1) DATA
has to be set to the appropriate value (LOW or HIGH) and a LOW to HIGH transition has to be
performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising
edges of CLK. The number of LOW to HIGH transitions on CLK during the HIGH period of EN is
used to determine the length of the command.
The bus protocol and the register addressing of ATR4256 are compatible to the addressing used
in ATR4255 and ATR4258. That means ATR4256 and ATR4255 (or ATR4258) can be operated
on the same 3-wire bus as shown in the application circuit.
12
ATR4256
4867D–AUDR–01/08
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