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参数资料
| 型号： | ATT3042-50T44I |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 现场可编程门阵列 |
| 文件页数： | 36/80页 |
| 文件大小： | 528K |
| 代理商： | ATT3042-50T44I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
36
Lucent Technologies Inc.
RCLK
During master parallel mode configuration,
RCLK
represents a read of an external dynamic
memory device (normally not used).
RDY/
BUSY
During peripheral parallel mode configuration, this pin indicates when the chip is ready for
another byte of data to be written to it. After configuration is complete, this pin becomes a user-
programmed I/O pin.
D[7:0]
This set of eight pins represents the parallel configuration byte for the parallel master and
peripheral modes. After configuration is complete, they are user-programmed I/O pins.
A[15:0]
This set of 16 pins presents an address output for a configuration EPROM during master parallel
mode. After configuration is complete, they are user-programmed I/O pins.
DIN
This user I/O pin is used as serial data input during slave or master serial configuration. This pin
is data zero input in master or peripheral configuration mode.
DOUT
This user I/O pin is used during configuration to output serial configuration data for daisy-
chained slaves’ data in.
TCLKIN
This is a direct CMOS level input to the global clock buffer.
I/O
Input/Output (Unrestricted)
. May be programmed by the user to be input and/or output pin
following configuration. Some of these pins present a high-impedance pull-up (see next page) or
perform other functions before configuration is complete (see above).
Pin Information
(continued)
Table 5. I/O Pins with Special Functions
(continued)
Symbol
Name/Description
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| ATT3042-50T68I | Field-Programmable Gate Arrays |
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| ATT3042-50T68I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Gate Arrays |
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| ATT3042-5J100I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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