参数资料
型号: ATTINY24A-MMHR
厂商: Atmel
文件页数: 67/135页
文件大小: 0K
描述: MCU AVR 2KB FLASH 20MHZ 20QFN
产品培训模块: MCU Product Line Introduction
tinyAVR Introduction
标准包装: 1
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 12
程序存储器容量: 2KB(1K x 16)
程序存储器类型: 闪存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-VFQFN 裸露焊盘
包装: 标准包装
其它名称: ATTINY24A-MMHRDKR
36
8183F–AVR–06/12
ATtiny24A/44A/84A
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. See “Internal Voltage
Reference” on page 41 for details on the start-up time.
7.4.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. See “Watchdog Timer” on page 41 for details on how to configure the Watchdog Timer.
7.4.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
both the I/O clock (clk
I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device
will be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. See the section “Digital Input Enable and Sleep Modes” on page 56 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
CC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). See
7.5
Register Description
7.5.1
MCUCR – MCU Control Register
The MCU Control Register contains control bits for power management.
Bit 7 – BODS: BOD Sleep
In order to disable BOD during sleep (see Table 7-1 on page 33) the BODS bit must be written to
logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,
both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be
set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is
set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for
the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.
In devices where Sleeping BOD has not been implemented this bit is unused and will always
read zero.
Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
Bit
76543210
BODS
PUD
SE
SM1
SM0
BODSE
ISC01
ISC00
MCUCR
Read/Write
R/W
Initial Value
00000000
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