参数资料
型号: ATTINY24A-SSUR
厂商: Atmel
文件页数: 20/135页
文件大小: 0K
描述: MCU AVR 2KB FLASH 20MHZ 14SOIC
产品培训模块: MCU Product Line Introduction
tinyAVR Introduction
标准包装: 1
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 12
程序存储器容量: 2KB(1K x 16)
程序存储器类型: 闪存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
包装: 标准包装
其它名称: ATTINY24A-SSURDKR
116
32015G–AVR32–09/09
AT32AP7001
12.4.2
Power Management
The RTC is continously clocked, and remains operating in all sleep modes except Static.
12.4.3
Interrupt
The RTC interrupt line is connected to one of the internal sources of the interrupt controller.
Using the RTC interrupt requires the interrupt controller to be programmed first.
12.4.4
Debug Operation
The RTC prescaler and watchdog timer are frozen during debug operation, unless the OCD sys-
tem keeps peripherals running in debug operation.
12.5
Functional Description
12.5.1
RTC operation
12.5.1.1
Source clock
The RTC is enabled by writing the EN bit in the CTRL register. This also enables the clock for
the prescaler. The PSEL bitfield in the same register selects the prescaler tapping, selecting the
source clock for the RTC:
f
RTC = 2
-(PSEL+1) * 32KHz
Note that if the RTC is used in stop mode, PSEL must be 2 or higher to ensure no ticks are
missed when entering or leaving sleep mode.
12.5.1.2
Counter operation
The RTC count value can be read from or written to the register VAL. The prescaler cannot be
written directly, but can be reset by writing the strobe PCLR in CTRL.
When enabled, the RTC will then up-count until it reaches 0xFFFFFFFF, and then wrap to 0x0.
Writing CTRL:TOPEN to one causes the RTC to wrap at the value written to TOP. The status bit
TOPI in ISR is set when this occurs.
12.5.1.3
RTC Interrupt
Writing the TOPI bit in IER enables the RTC interrupt, while writing the corresponding bit in IDR
disables the RTC interrupt. IMR can be read to see whether or not the interrupt is enabled. If
enabled, an interrupt will be generated if the TOPI flag in ISR is set. The flag can be cleared by
writing TOPI in ICR to one.
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