参数资料
型号: ATTINY44A-SSUR
厂商: Atmel
文件页数: 3/135页
文件大小: 0K
描述: MCU AVR 4KB FLASH 20MHZ 14SOIC
产品培训模块: MCU Product Line Introduction
tinyAVR Introduction
标准包装: 1
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 12
程序存储器容量: 4KB(2K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
包装: 标准包装
其它名称: ATTINY44A-SSURDKR
100
32015G–AVR32–09/09
AT32AP7001
11.5.6.2
Supported sleep modes
The following sleep modes are supported. These are detailed in Table 11-2.
Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupt,
or WAKE_N pin.
Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources
are any interrupt from PB modules, or WAKE_N pin.
Standby: All synchronous clocks are stopped, but oscillators and PLL’s are running, allowing
quick wake-up to normal mode. Wake-up sources are RTC or external interrupt, or WAKE_N
pin.
Stop: As Standby, but Oscillator 0 and 1, and the PLL’s are stopped. 32 KHz oscillator and
RTC/WDT still operates. Wake-up sources are RTC or external interrupt, or WAKE_N pin.
Static: All oscillators and clocks are stopped. Wake-up sources are external interrupt or
WAKE_N pin.
11.5.6.3
Precautions when entering sleep mode
Modules communicating with external circuits should normally be disabled before entering a
sleep mode that will stop the module operation. This prevents erratic behavior when entering or
exiting sleep mode. Please refer to the relevant module documentation for recommended
actions.
Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. This means that bus transactions are not allowed between clock domains affected
by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus
transaction.
The CPU and caches are automatically stopped in a safe state to ensure that all CPU bus oper-
ations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no
further action is necessary.
When entering a deeper sleep mode than Idle mode, all other HSB masters must be stopped
before entering the sleep mode. Also, if there is a chance that any PB write operations are
incomplete, the CPU should perform a read operation from any register on the PB bus before
executing the sleep instruction. This will stall the CPU while waiting for any pending PB opera-
tions to complete.
The Power manager will normally turn of all debug related clocks in the system in the static sleep
mode, m aking it impossible for a debugger to comm unicate with the system . If a
Table 11-2.
Sleep modes
Index
Sleep Mode
CPU
HSB
PBA,B +
GCLK
Osc0,1 +
PLL0,1
Osc32 +
RTC/WDT
0
Idle
Off
On
1
Frozen
Off
OffOnOnOn
2
Standby
Off
On
3
Stop
Off
On
5
Static
Off
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