参数资料
型号: ATTINY48-MMUR
厂商: Atmel
文件页数: 20/26页
文件大小: 0K
描述: MCU AVR 4KB FLASH 12MHZ 28MLF
标准包装: 1
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 12MHz
连通性: I²C,SPI
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 24
程序存储器容量: 4KB(2K x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 6x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-VFQFN 裸露焊盘
包装: 标准包装
其它名称: ATTINY48-MMURDKR
3
8008HS–AVR–04/11
ATtiny48/88
1.1
Pin Descriptions
1.1.1
VCC
Digital supply voltage.
1.1.2
AVCC
AV
CC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should
be externally connected to V
CC even if the ADC is not used. If the ADC is used, it is recom-
mended this pin is connected to V
CC through a low-pass filter, as described in “Analog Noise
Canceling Techniques” on page 172.
The following pins receive their supply voltage from AV
CC: PC7, PC[5:0] and (in 32-lead pack-
ages) PA[1:0]. All other I/O pins take their supply voltage from V
CC.
1.1.3
GND
Ground.
1.1.4
Port A (PA3:0)
Port A is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PA[3:0] output buffers have symmetrical drive characteristics with both sink and source capabil-
ity. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors
are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the
clock is not running.
This port is available in 32-lead TQFP, 32-pad QFN and 32-ball UFBGA packages, only.
1.1.5
Port B (PB7:0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both sink and source capability.
As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are
activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the internal clock
operating circuit.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
69.
1.1.6
Port C (PC7, PC5:0)
Port C is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC7 and PC[5:0] output buffers have symmetrical drive characteristics with both sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
1.1.7
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-
acteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for
longer than the minimum pulse width will generate a reset, even if the clock is not running. The
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