参数资料
型号: ATV2500B-15KC
厂商: Atmel
文件页数: 2/21页
文件大小: 0K
描述: IC CPLD 15NS CERAMIC 44JLCC
标准包装: 27
系列: ATV2500B(L) 和 BQ(L)
可编程类型: UV 可擦除
最大延迟时间 tpd(1): 15.0ns
电压电源 - 内部: 4.75 V ~ 5.25 V
宏单元数: 24
输入/输出数: 24
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.58x16.58)
包装: 管件
其它名称: ATV2500B15KC
ATV2500B(Q)(L)
10
Input Test Waveforms and
Measurement Levels
Output Test Load
Preload and Observability of Registered Outputs
The ATV2500Bs registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A V
IH level on the odd I/O pins will force the
appropriate register high; a V
IL will force it low, independent
of the polarity or other configuration bit settings.
The PRELOAD state is entered by placing an 10.25V to
10.75V signal on SMP lead 42. When the preload clock
SMP lead 23 is pulsed high, the data on the I/O pins is
placed into the 12 registers chosen by the Q select and
even/odd select pins.
Register 2 observability mode is entered by placing an
10.25V to 10.75V signal on pin/lead 2. In this mode, the
contents of the buried register bank will appear on the
associated outputs when the OE control signals are active.
AC Characteristics
Symbol
Parameter
-12
-15
-20
-25
-30
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tPD1
Input to Non-registered Output
12
15
20
25
30
ns
t
PD2
Feedback to Non-registered
Output
12
15
20
25
30
ns
tPD3
Input to Non-registered Feedback
8
11
15
18
20
ns
t
PD4
Feedback to Non-registered
Feedback
811
15
18
20
ns
tEA1
Input to Output Enable
12
15
20
25
30
ns
t
ER1
Input to Output Disable
12
15
20
25
30
ns
t
EA2
Feedback to Output Enable
12
15
20
25
30
ns
tER2
Feedback to Output Disable
12
15
20
25
30
ns
t
AW
Asynchronous Reset Width
6
8
12
15
18
ns
t
AP
Asynchronous Reset to
Registered Output
15
18
22
28
30
ns
t
APF
Asynchronous Reset to
Registered Feedback
12
15
19
25
30
ns
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