
Axcelerator Family FPGAs
v2.8
2-55
Global Resources
One of the most important aspects of any FPGA
architecture is its global resources or clocks. The
Axcelerator family provides the user with flexible and
easy-to-use global resources, without the limitations
normally found in other FPGA architectures.
The AX architecture contains two types of global
resources, the HCLK (hardwired clock) and CLK (routed
clock). Every Axcelerator device is provided with four
HCLKs and four CLKs for a total of eight clocks,
regardless of device density.
Hardwired Clocks
The hardwired (HCLK) is a low-skew network that can
directly drive the clock inputs of all sequential modules
(R-cells, I/O registers, and embedded RAM/FIFOs) in the
device with no antifuse in the path. All four HCLKs are
available everywhere on the chip.
Timing Characteristics
Table 2-69 AX125 Dedicated (Hardwired) Array Clock Networks
Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C
'–2' Speed
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Networks
tHCKL
Input Low to High
3.02
3.44
4.05
ns
tHCKH
Input High to Low
3.03
3.46
4.06
ns
tHPWH
Minimum Pulse Width High
0.58
0.65
0.77
ns
tHPWL
Minimum Pulse Width Low
0.52
0.59
0.69
ns
tHCKSW
Maximum Skew
0.06
0.07
0.08
ns
tHP
Minimum Period
1.15
1.31
1.54
ns
tHMAX
Maximum Frequency
870
763
649
MHz
Table 2-70 AX250 Dedicated (Hardwired) Array Clock Networks
Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C
'–2' Speed
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Networks
tHCKL
Input Low to High
2.57
2.93
3.45
ns
tHCKH
Input High to Low
2.61
2.97
3.50
ns
tHPWH
Minimum Pulse Width High
0.58
0.65
0.77
ns
tHPWL
Minimum Pulse Width Low
0.52
0.59
0.69
ns
tHCKSW
Maximum Skew
0.06
0.07
0.08
ns
tHP
Minimum Period
1.15
1.31
1.54
ns
tHMAX
Maximum Frequency
870
763
649
MHz