参数资料
型号: BA6247FP-YE2
厂商: Rohm Semiconductor
文件页数: 7/14页
文件大小: 0K
描述: IC DVR REVERSE MOTOR 25HSOP
标准包装: 2,000
应用: 直流电机驱动器
输出数: 2
电流 - 输出: 1A
电源电压: 8 V ~ 18 V
工作温度: -25°C ~ 75°C
安装类型: 表面贴装
封装/外壳: 25-SOP(0.213",5.40mm)+ 2 翼片
供应商设备封装: 25-HSOP
包装: 带卷 (TR)
BA6247FP-Y,BA6238A
Technical Note
2)
Output high voltage setting
This function optionally sets output voltage by the VR pin and controls the motor rotating speed. However, when the
output high voltage is set to a low level, consumption at IC increases. Carry out thermal design with sufficient margin
incorporated with the power dissipation (Pd) under the actual application condition taken into account. Please do not to
exceed the VCC1 and VCC2 voltage forced to the VR pin voltage.
a) BA6247FP-Y
The circuit diagram associated with the output high voltage setting VR pin is as per shown on the right.
The output high and low voltages V OH and V OL are expressed by:
VCC1
V OH = VR + ( V F(Q5) + V F(Q4) ) - ( V F(Q2) + V F(Q3) )
V OH ≈ VR
V OL = V SAT(Q7) + V F(Q6)
(Reference values; V SAT ≈ 0.2V, V F ≈ 0.7V)
In addition, the relation of VREF voltage to output voltage
is expressed by:
VR
Q1
Q4
Q5
Q2
Q7
Q3
Q6
VCC2
OUT
GND
VR < VCC1 - V SAT(Q1) - V F(Q4) - V F(Q5)
VR < VCC2 - V SAT(Q3) + (V F(Q2) +V F(Q3) ) - ( V F(Q4) + V F(Q5) )
Fig.13 BA6247FP-Y
Therefore, when the VR voltage condition is as follows, the output high voltage is restricted.
VR > VCC1 - V SAT(Q1) - V F(Q4) - V F(Q5)
VR > VCC2 - V SAT(Q3) + (V F(Q2) +V F(Q3) ) - ( V F(Q4) + V F(Q5) )
V OH = VCC1 - V SAT(Q1) - V F(Q2) - V F(Q3)
V OH = VCC2 - V SAT(Q3)
b) BA6238A
The circuit diagram associated with the output high voltage setting VR pin is as per shown on the right.
The output high and low voltages V OH and V OL are expressed by:
V OH = VR + ( V F(Q5) + V F(Q4) ) - ( V F(Q2) + V F(Q3) )
V OH ≈ VR
V OL = V SAT(Q7) + V F(Q6)
Q1
Q2
VCC1
VCC2
(Reference values; V SAT ≈ 0.1V, V F ≈ 0.7V)
In addition, the relation of VREF voltage to output voltage is expressed by:
VR < VCC1 - V SAT(Q1) - V F(Q4) - V F(Q5)
Q4
Q5
Q7
Q3
Q6
OUT
VR < VCC2 - ( V SAT(Q2) + V F(Q3) ) + (V F(Q2) + V F(Q3) ) - ( V F(Q4) + V F(Q5) )
VR
GND
Therefore, when the VREF voltage condition is as follows, the output high
voltage is restricted.
VR > VCC1 - V SAT(Q1) - V F(Q4) - V F(Q5)
VR > VCC2 - ( V SAT(Q2) + V F(Q3) ) + (V F(Q2) + V F(Q3) ) - ( V F(Q4) + V F(Q5) )
V OH = VCC1 - V SAT(Q1) - V F(Q2) - V F(Q3)
V OH = VCC2 - V SAT(Q2) - V F(Q3)
Fig.14 BA6238A
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? 2011 ROHM Co., Ltd. All rights reserved.
7/11
2011.05 - Rev.B
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