参数资料
型号: BD00GA3WEFJ-E2
厂商: Rohm Semiconductor
文件页数: 10/14页
文件大小: 0K
描述: IC REG LDO ADJ .3A 8-HTSOP
特色产品: CMOS LDO Regulators
标准包装: 1
稳压器拓扑结构: 正,可调式
输出电压: 1.5 V ~ 13 V
输入电压: 4.5 V ~ 14 V
电压 - 压降(标准): 0.6V @ 300mA
稳压器数量: 1
电流 - 输出: 300mA(最小值)
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
供应商设备封装: 8-HTSOP-J
包装: 标准包装
其它名称: BD00GA3WEFJ-E2DKR
BD00GA3WEFJ
Technical Note
(11). Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC.
The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage.
Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate)
voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
Pin A
Pin B
C
B
Pin B
Pin A
E
P +
N
P +
N
P P +
N
P substrate
GND
Parasitic
element
N
Parasitic element
N
P P +
N
P substrate
GND GND
B C
E
Parasitic
element
GND
Other adjacent elements
(12). Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a
single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by
large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any
external components, either.
www.rohm.com
? 2010 ROHM Co., Ltd. All rights reserved.
10/11
2010.04 - Rev.A
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