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参数资料
| 型号： | BD6637KV-E2 |
| 元件分类： | 运动控制电子 |
| 英文描述： | DISK DRIVE MOTOR CONTROLLER, 1 A, PQFP64 |
| 封装： | ROHS COMPLIANT, VQFP-64 |
| 文件页数： | 12/17页 |
| 文件大小： | 763K |
| 代理商： | BD6637KV-E2 |
4/16
BD6637KV/KS
(Unless otherwise specified Ta=25
,VCC=3V, C_VM
D_VM
L_VM=5V
UNREG=7.2V)
Parameter
Symbol
Limit
Unit
Conditions
Fig No.
Min.
Typ.
Max.
<CYLINDER STARTING/DETECTION/SLOPE>
DETECT terminal charge current
D_IDETO
2
5
10
A
Fig.12
DETECT terminal discharge current
D_IDETI
2
5
10
A
Fig.12
DETECT terminal H voltage
D_VDETH
1.1
1.3
1.5
V
Fig.13
DETECT terminal L voltage
D_VDETL
0.5
0.65
0.8
V
Fig.13
ISET voltage
D_VISET
0.32
0.4
0.48
V
RD_ISET=18k
Fig.14
SL1,2 charge current
D_ISLO
16
22
28
A
RD_ISET=18k
Fig.15
SL1,2 discharge current
D_ISLI
17
24
31
A
RD_ISET=18k
Fig.15
SL1,2 H voltage
D_VSLH
2.5
2.8
V
Fig.16
SL1,2 L voltage
D_VSLL
0.85
1
1.15
V
Fig.16
SL1,2 charge and discharge
current ratio
D_RSL
0.82
0.89
0.96
SL switching EC level
D_VECSL
1.6
2
2.4
V
< CYLINDER VS>
Voltage gain
D_GVS
7
8
9
TIMES
Output H voltage
D_VVSOH
0.5
0.8
V
IOVS=1mA,
between VCC and output
Output L voltage
D_VVSOL
0.13
0.2
V
IOVS=50
A
VS offset voltage
D_VVSOFS
0.12
0.25
0.38
V
DC/DC
3 in use
<CYLINDER FGAMP>
Input offset voltage
D_VFGOFS
-12
12
mV
DC bias voltage
D_VFG+
1.3
1.5
1.7
V
Voltage gain 1
D_FAV1
50
59
dB
f=3kHz
Fig.20
Voltage gain 2
D_FAV2
30
36
dB
f=50kHz
Fig.20
In-phase input voltage range
D_VFGCM
0.35
VCC-1.1
V
Output H voltage
D_VFGAOH
0.3
0.5
V
IOH=-0.2mA,
between VCC and output
Output L voltage
D_VFGAOL
0.15
0.35
V
IOL=1mA
<CYLINDER FGHYS>
D_FG hysteresis width
D_VFGHYS
r84
r110
r136
mV
Measure D_FGAMP at 1K
feed back resistance
Fig.24
DC bias voltage
D_VFG+
1.3
1.5
1.7
V
Measure D_FGAMP at 1K
feed back resistance
Output L voltage
D_VFGSOL
0.1
0.3
V
IOL=1mA
Fig.21
<CYLINDER PGAMP>
Input offset voltage
D_VPGOFS
-12
17
mV
DC bias voltage
D_VPG+
1.3
1.5
1.7
V
Voltage gain 1
D_PAV1
50
59
dB
f=3kHz
Fig.20
Voltage gain 2
D_PAV2
30
36
dB
f=50kHz
Fig.20
In-phase input voltage range
D_VPGCM
0.35
VCC-1.1
V
Output H voltage
D_VPGAOH
0.3
0.5
V
IOH=-0.2mA,
between VCC and output
Output L voltage
D_VPGAOL
0.15
0.35
V
IOL=1mA
<CYLINDER PGHYS>
D_PG hysteresis width
D_VPGHYS
r118
r144
r170
mV
Fig.23
DC bias voltage
D_VPG+
1.3
1.5
1.7
V
Output L voltage
D_VPGSOL
0.1
0.3
V
IOL=1mA
Fig.21
<LOADING>
Output saturation voltage
L_VSAT
0.3
0.5
V
IOUT=200mA,L_REF=L_VM
Total saturation voltage of low and
high side output transistor
Fig.
17,18
L_REF pin input current
L_IIREF
0.3
2
A
Vout-L_REF offset
L_VOFS
0
100
200
mV
Fig.19
Forward rotation control
voltage range
L_VFWD
0.7
V
Brake voltage range
L_VBRK
1.3
1.5
1.7
V
Reverse rotation control
voltage range
L_VREV
2.3
V
L_REF output open voltage
L_VREF
1.3
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