参数资料
型号: BD8964FVM-TR
厂商: Rohm Semiconductor
文件页数: 13/18页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 1.2A MSOP8
标准包装: 3,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1 V ~ 1.8 V
输入电压: 4 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 1.2A
同步整流器:
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-VSSOP,8-MSOP(0.110",2.80mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-MSOP
BD8964FVM
Datasheet
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
fp=
fz (ESR) =
Gain
[dB]
A
0
I OUT Min.
fp(Max.)
I OUT Max.
fz(ESR)
1
2π×R O ×C O
1
2π×E SR ×C O
Pole at power amplifier
Phase
[deg]
0
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
-90
Fig.29 Open loop gain characteristics
fp (Min.) =
fp (Max.) =
1
2π×R OMax. ×C O
1
2π×R OMin. ×C O
[Hz]←with lighter load
[Hz] ←with heavier load
A
fz(Amp.)
Gain
[dB]
Phase
[deg]
0
0
-90
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This is
because when the capacitance is doubled, the capacitor ESR
reduces to half.)
Fig.30 Error amp phase compensation characteristics
fz (Amp.) =
1
2π×R ITH ×C ITH
V CC
Cin
EN
V CC ,PV CC
SW
L
V OUT
V OUT
V OUT
ITH
GND,PGND
ESR
C O
R O
R ITH
C ITH
Fig.31 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz (Amp.) = fp (Min.)
1
2π×R ITH ×C ITH
=
1
2π×R OMax. ×C O
5. Determination of output voltage
The output voltage V OUT is determined by the equation (7):
V OUT =(R2/R1+1) × V ADJ ??? (7) V ADJ : Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
(Adjustable output voltage range : 1.0V to 1.8V)
Use 1 k? to 100 k? resistor for R1. If a resistor of the resistance higher than
100 k? is used, check the assembled set carefully for ripple voltage etc.
6
1
SW
ADJ
4.7μH
10μF
R2
R1
Output
Fig.32 Determination of output voltage
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? ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
13/16
TSZ02201-0J3J0AJ00050-1-2
02.MAR.2012 Rev.001
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