参数资料
| 型号： | BD9851EFV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 8/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST INV HTSSOP-B20 |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 3MHz |
| 电源电压： | 4 V ~ 18 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 是 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-VSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1373 (CN2011-ZH PDF) |
| 其它名称： | BD9851EFV-E2DKR |
Description of operations
1) Reference voltage block
The reference voltage block generates a constant voltage with temperature compensated through inputting the power supplied from
the Vcc pin. The output voltage is 2.5 V, with a ±1% accuracy. To cancel noises, insert a capacitor with a low ESR (several tens of mΩ)
between the V REF and GND pins. It is recommended to use a ceramic capacitor of 1μF for this purpose.
2) Triangular wave oscillator block
By connecting the resistor and capacitor of frequency settings to the RT and CT pins (only to RT pin on the BD9850FVM), a triangular
wave will be generated and then input to the PWM comparators of Channels 1 and 2.
3) Error Amp block
The Error Amp block detects the output voltage of the INV pin, amplifies an error with the set output voltage, and then outputs the
error from the FB pin. The comparison voltage is 1 V, with a ±2% accuracy. (The Channel 2 of the BD9851EFV uses the NON pin input
voltage as a reference.)
Inserting a resistor and capacitor between the INV and FB pins will conduct phase compensation.
4) PWM comparator block
The PWM comparator block converts the output voltage (FB voltage) into a PWM waveform and outputs it to the FET driver.
<Dead time control> (Only available on the BD9851EFV)
Inputting a voltage, divided by resistance of the VREF pin in the DTC pin, will allow maximum ON duty setting.
<Soft start (BD9850FVM)>
Inserting a capacitor between the CTL/SS and GND pins will allow the soft start function to control the rising output voltage.
<Soft start (BD9851EFV)>
Inserting a capacitor between the DTC and GND pins will allow the soft start function to control the rising output voltage.
Furthermore, the overshoot of output voltage at startup can be derated. Adding a Schottky diode between the FB and DTC
pins will make it possible to suppress the overshoot rate (only available with step-down application).
5) FET driver block
This block is a push-pull type driver enabling direct drive of external MOS FET.
<Setting of step-down/step-up switching (Only available for Channel 1 of BD9851EFV)>
For the Channel 1, SEL1 pin setting will determine the application function.
Set the SEL1 pin to step-down (P-ch drive) mode for short-circuiting Vcc or to step-up (N-ch drive) mode for short-circuiting GND.
Furthermore, be sure to short-circuit the SEL1 pin to Vcc or GND pin.
6) Standby function
(BD9850FVM)
The CTL/SS pin allows for output ON/OFF control. Set the CTL/SS pin voltage to “H” to activate the output ON control.
(BD9851EFV)
The STB pin allows for output ON/OFF control. Set the STB pin voltage to “H” to activate the output ON control.
The standby mode circuit current should be set to less than 5 μA.
7) Short circuit protection circuit (SCP) (Only available on BD9851EFV)
The SCP is a timer-latch type short circuit protection circuit.
If the output voltage of either channel drops below the set voltage, the Error Amp will be activated to increase the FB voltage and
initiate charging the capacitor connected to the SCP pin with a 2 μA current. When the SCP pin voltage exceeds 1.5 V, the latch circuit
will be activated to fix the output of both channels at OFF and, at the same time, the DTC pin at “L” level.
In order to rest the latch circuit, set the STB pin to “L” level once, and then to “H” level. Or, turn ON the power supply again.
Furthermore, if the short circuit protection circuit is not used, short-circuit the SCP pin to the GND pin.
8) Under Voltage Lock Out (UVLO) circuit
The UVLO is a protection circuit to prevent the IC from malfunctioning when the power supply turns ON or if an instantaneous power
interruption occurs.
When the Vcc voltage falls below 3.8 V (or 3.7 V on the BD9851EFV), the output of both channels will be fixed at “OFF” and, at the same
time, the DTC pin at “L” level. Hysteresis width of 0.1 V (or 0.11 V on the BD9851EFV) is provided for the detection voltage and release
voltage of the UVLO in order to prevent malfunctions of the IC which may result from variations in the input voltage due to threshold
online.
Furthermore, if the latch circuit is activated through the short circuit protection circuit, the circuit will be reset by this UVLO.
9) Thermal shutdown circuit (TSD)
The TSD is a protection circuit to prevent the destruction of the IC due to abnormal heat generation.
If the TSD detects an abnormal heat generation (175?C) on the chip, the output of both channels will be fixed at “OFF” and, at the same
time, the DTC pin at “L” level. Hysteresis width (15?C) is provided for the superheat detection and release temperatures in order to prevent
malfunctions of the IC which may result from variations in the input voltage due to threshold online.
Furthermore, if the latch circuit is activated through the short circuit protection circuit, the circuit will be reset by this TSD.
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