参数资料
| 型号： | BH7824FVM-FTR |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | IC AMP AUDIO .5W MONO AB 8MSOP |
| 标准包装： | 1 |
| 类型： | AB 类 |
| 输出类型： | 1-通道（单声道） |
| 在某负载时最大输出功率 x 通道数量： | 500mW x 1 @ 8 欧姆 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 特点： | 消除爆音，关机，热保护 |
| 安装类型： | 表面贴装 |
| 供应商设备封装： | 8-MSOP |
| 封装/外壳： | 8-VSSOP，8-MSOP（0.110"，2.80mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1375 (CN2011-ZH PDF) |
| 其它名称： | BH7824FVM-FDKR |
Micrel, Inc.
SY100EP14AU
June 2010
3
M9999-061110-A
hbwhelp@micrel.com
Pin Description
Pin Number
Pin Name
Pin Function
13, 14
16, 17
CLK0, /CLK0
CLK1, /CLK1
LVPECL, LVECL, HSTL Clock or Data Inputs. Internal 75k pull-down resistors on CLK0, CLK1,
and internal 75k pull-up and 75k pull-down resistors on /CLK0, /CLK1. For single-ended
applications, connect signal into CLK0 and/or CLK1 inputs. /CLK0, /CLK1 default condition is
VCC/2 when left floating. CLK0, CLK1 default condition is LOW when left floating.
1, 2, 3, 4
5, 6, 7, 8
9, 10
Q0, /Q0, Q1, /Q1
Q2, /Q2, Q3, /Q3
Q4, /Q4
LVPECL/LVECL Differential Outputs: Terminate with 50 to VCC-2V. For single-ended
applications, /Q0 to /Q4 terminate the unused output with 50 to VCC-2V.
19
/EN
LVPECL/LVECL compatible synchronous enable: When /EN goes HIGH, the QOUT will go LOW
and /QOUT will go HIGH on the next LOW input clock transition. Includes a 75k pull-down.
Default state is LOW when left floating. The internal latch is clocked on the falling edge of the
input clock (CLK0, CLK1).
12
SEL
LVPECL/LVECL compatible 2:1 MUX input signal select: When SEL is LOW, CLK0 input pair is
selected. When SEL is HIGH, CLK1 input pair is selected. Includes a 75k pull-down. Default
state is LOW and CLK0 is selected.
15
VBB
Output Reference Voltage: Equal to VCC-1.4V (approx.), and used for single-ended input signals
or AC-coupled applications. For single-ended LVPECL and LVECL applications, bypass with a
0.01F to VCC. Max. sink/source current is 0.5mA.
18, 20
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors.
11
VEE
Negative Power Supply: LVPECL applications, connect to GND.
Truth Table
CLK0
CLK1
CLK_SEL
/EN
Q
L
X
L
H
X
L
H
X
L
H
L
X
H
L
H
X
H
L
Note:
1.
On next negative transition of CLK0 or CLK1.
Function Table
CLK_SEL
Active Input
0
CLK0, /CLK0
1
CLK1, /CLK1
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