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参数资料
| 型号： | BN87C51FA12 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 16/18页 |
| 文件大小： | 254K |
| 代理商： | BN87C51FA12 |
AUTOMOTIVE 87C51FAFBFCFC-20
DESIGN CONSIDERATION
When the Idle mode is terminated by a hardware
reset the device normally resumes program execu-
tion from where it left off up to two machine cycles
before the internal reset algorithm takes control On-
chip hardware inhibits access to internal RAM in this
event but access to the port pins is not inhibited To
eliminate the possibility of an unexpected write when
Idle is terminated by reset the instruction following
the one that invokes Idle should not be one that
writes to a port pin or to external memory
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing
and
debugging
of
systems
using
the
87C51FAFBFC without removing it from the cir-
cuit The ONCE Mode is invoked by
1 Pull ALE low while the device is in reset and
PSEN is high
2 Hold ALE low as RST is deactivated
While the device is in ONCE Mode the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high The oscillator circuit remains ac-
tive While the 87C51FAFBFC is in this mode an
emulator or test CPU can be used to drive the circuit
Normal operation is restored when a normal reset is
applied
RFI REDUCTION MODE
The RFI reduction feature can be used only if exter-
nal program memory is not required since this mode
disables the ALE pin during instruction code fetches
By writing a logical one to the LSB of the Auxiliary
Register (address 08EH) the ALE is disabled for in-
struction code fetches and the output is weakly held
high When a logical zero is written the ALE pin is
enabled allowing it to generate the Address Latch
Enable signal This bit is cleared by reset Once dis-
abled ALE remains disabled until it is reset by soft-
ware or until a hardware reset occurs
Table 2 Status of the External Pins during Idle and Power Down
Mode
Program
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Memory
Idle
Internal
1
Data
Idle
External
1
Float
Data
Address
Data
Power Down
Internal
0
Data
Power Down
External
0
Float
Data
NOTE
For more detailed information on the reduced power modes refer to current Embedded Applications Handbook and Applica-
tion Note AP-252 ‘‘Designing with the 80C51BH’’
7
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