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参数资料
| 型号： | BP87C51FB |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 15/18页 |
| 文件大小： | 1527K |
| 代理商： | BP87C51FB |
AUTOMOTIVE 87C51FA/FB/FC/FC-20
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 5. There are no requirements on the
duty cycle of the external clock signal, since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets VIL and
VIH specifications the capacitance will not exceed
20 pF.
270961±5
C1, C2 e 30 pF g10 pF for Crystals
For Ceramic Resonators, contact resonator manufac-
turer.
Figure 4. Oscillator Connections
270961±6
Figure 5. External Clock Drive Configuration
IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consump-
tion is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated.
On the 87C51FA/FB/FC either a hardware reset or
external interrupt can cause an exit from Power
Down. Reset redefines all the SFRs but does not
change the on-chip RAM. An external interrupt al-
lows both the SFRs and the on-chip RAM to retain
their values.
To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before VCC is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
With an external interrupt. INT0 or INT1 must be en-
abled and configured as level-sensitive. Holding the
pin low restarts the oscillator (the oscillator must be
allowed time to stabilize after start up, before this pin
is released high) but bringing the pin back high com-
pletes the exit. Once the interrupt is serviced, the
next instruction to be executed after RETI will be the
one following the instruction that put the device into
Power Down.
6
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