参数资料
型号: BQ3285S
厂商: TEXAS INSTRUMENTS INC
元件分类: XO, clock
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO24
封装: 0.300 INCH, PLASTIC, SOIC-24
文件页数: 24/26页
文件大小: 676K
代理商: BQ3285S
Periodic Interrupt
The mux output used to drive the SQW output also
drives the interrupt-generation circuitry. If the periodic
interrupt event is enabled by writinga1tothe periodic
interrupt enable bit (PIE) in register C, an interrupt re-
quest is generated once every 122
s to 500ms. The pe-
riod between interrupts is selected by the same bits in
register A that select the square wave frequency (see Ta-
ble 3).
Alarm Interrupt
During each update cycle, the RTC compares the hours,
minutes, and seconds bytes with the three corresponding
alarm bytes. If a match of all bytes is found, the alarm
interrupt event flag bit, AF in register C, is set to 1. If
the alarm event is enabled, an interrupt request is gen-
erated.
An alarm byte may be removed from the comparison by
setting it to a “don’t care” state. An alarm byte is set to
a “don’t care” state by writinga1toeachofitstwo
most-significant bits. A “don’t care” state may be used to
select the frequency of alarm interrupt events as follows:
n
If none of the three alarm bytes is “don’t care,” the
frequency is once per day, when hours, minutes, and
seconds match.
n
If only the hour alarm byte is “don’t care,” the
frequency is once per hour, when minutes and
seconds match.
n
If only the hour and minute alarm bytes are “don’t
care,” the frequency is once per minute, when seconds
match.
n
If the hour, minute, and second alarm bytes are
“don’t care,” the frequency is once per second.
Update Cycle Interrupt
The update cycle ended flag bit (UF) in register C is set
toa1attheendofan update cycle. If the update inter-
rupt enable bit (UIE) of register B is 1, and the update
transfer inhibit bit (UTI) in register B is 0, then an in-
terrupt request is generated at the end of each update
cycle.
Accessing RTC bytes
Time and calendar bytes read during an update cycle
may be in error. Three methods to access the time and
calendar bytes without ambiguity are:
n
Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).
n
Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of tBUC
time to access the clock bytes (see Figure 3).
n
Use
the
periodic
interrupt
event
to
generate
interrupt requests every tPI time, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of
tPI/2+tBUC
time to access the clock bytes (see Figure 3).
Oscillator Control
When power is first applied to the bq3285 and VCC is
above VPFD, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of 11X turns the oscillator on,
but keeps the frequency divider disabled. Any other pat-
tern to these bits keeps the oscillator off.
7
Figure 3. Update-Ended/Periodic Interrupt Relationship
bq3285
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相关代理商/技术参数
参数描述
BQ3285S- 制造商:TI 制造商全称:Texas Instruments 功能描述:Real-Time Clock RTC
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BQ3285S-SB2G4 功能描述:实时时钟 RTC IC with 114x8 NVSRAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube
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