参数资料
| 型号： | BR24T01F-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 13/22页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM I2C 1K 400KHZ 8-SOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1K (128 x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-SOP |
| 包装： | 标准包装 |
| 其它名称： | BR24T01F-WE2DKR |
BR24T □□□□ Series
Technical Note
● WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel
valid area. And, after execution of forced end by WP, standby status gets in.
? Rise of D0 taken clock
SCL
SCL
? Rise of SDA
SDA
D1
D0
ACK
SDA
D0
ACK
Enlarged view
Enlarged view
K address
SDA
S
T Slave
A
R address
T
A
C Word
L
A
C D7 D6 D5 D4 D3 D2 D1 D0
K
L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
WP cancel invalid area
WP cancel valid area
WP cancel invalid area
WP
Data is not written.
Fig.50 WP valid timing
● Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.51)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.51 Case of cancel by start, stop condition during slave address input
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
13/21
2011.03 - Rev.A
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