参数资料
型号: BR93L46RFVT-WE2
厂商: Rohm Semiconductor
文件页数: 14/41页
文件大小: 0K
描述: IC EEPROM 1KBIT 2MHZ 8-TSSOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1K (64 x 16)
速度: 2MHz
接口: Microwire 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP-B
包装: 标准包装
其它名称: BR93L46RFVT-WE2DKR
BR93L -W Series, 93A □□ -WM Series, BR93H □□ -WC Series
● Application
1) Method to cancel each command
○ READ
Technical Note
Start bit
1bit
Ope code
2bit
Address
6bit
*1
Data
16bit
(In the case of BR93L46-W/A46-WM )
Cancel is available in all areas in read mode.
? Method to cancel : cancel by CS=“L”
Fig.66 READ cancel available timing
* 1 Address is 8 bits in BR93L56-W/A56-WM, BR93L-66W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM, BR93L86-W/A86-WM
○ WRITE, WRAL
? 25 Rise of clock
*2
SK
DI
24
D1
25
D0
Enlarged figure
Start bit
Ope code
Address
*1
Data
tE/W
(In the case of BR93L46-W/A46-WM )
1bit
2bit
a
6bit
16bit
b
a : From start bit to 25 clock rise * 2
Cancel by CS=“L”
*1
Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM BR93L86-W/A86-WM
*2 27 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM
b : 25 clock rise and after * 2
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
29 clocks in BR93L76-W/A76-WM BR93L86-W/A86-WM
29 Rise of clock
*2
SK
DI
D1
a
28
29
D0
b
30
31
c
Enlarged figure
Start bit
1bit
Ope code
2bit
Address *1
10bit
Data
16bit
tE/W
(In the case of BR93L86-W/A86-WM )
a : From start bit to 29 clock rise
Cancel by CS=“L”
b : 29 clock rise and after
a
b
c
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
c : 30 clock rise and after
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is output continuously is not available.
Fig.67 WRITE, WRAL cancel available timing
Note 1) If Vcc is made OFF in this area, designated address data is
not guaranteed, therefore write once again.
Note 2) If CS is started at the same timing as that of the SK rise,
write execution/cancel becomes unstable, therefore, it is
recommended to fail in SK=”L” area.
As for SK rise, recommend timing of tCSS/tCSH or higher.
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
14/40
2011.09 - Rev.G
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