参数资料
型号: BT497AKHF160
厂商: CONEXANT SYSTEMS
元件分类: 显示控制器
英文描述: 1280 X 1024 PIXELS PALETTE-DAC DSPL CTLR, PQFP160
封装: PLASTIC, QFP-160
文件页数: 1/141页
文件大小: 1512K
代理商: BT497AKHF160
Data Sheet
Preliminary Information/Conexant Proprietary and Confidential
L498A_B
June 17, 1999
Advance Information
This document contains information on a product under development.
The parametric information contains target parameters that are subject to change
.
Bt497A/498A
240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC
The Bt497A/8A is designed specifically for high-performance, high-resolution color
graphics applications. The architecture enables the display of true-color 1920 x 1200
bit-mapped color graphics at 75 Hz refresh rates. The wide input pixel port and internal
multiplexing modes enable TTL-compatible interfacing to the frame buffer, while
maintaining PLL-generated 240 MHz, or externally provided 240 MHz video data rates
required for high-refresh-rate, high-resolution color graphics.
The Bt497A/8A supports PLL pixel clock generation, supporting a variety of
frequencies using an M/N divisor scheme. This decreases system cost due to the
elimination of multiple crystal oscillators that are used to support a variety of monitor
and refresh rates.
The Bt497A/8A contains three 1K x 8 color lookup tables for color-space flexibility,
triple 8-bit video D/A converters, a 64 x 64 x 2 programmable cursor, and a fully
programmable video timing generator.
The Bt497A/8A RAMDAC allows different display modes of operation for each pixel.
Utilizing a window-type scheme, each set of pixel and control bits maps the
accompanying pixel data to a user-defined display mode. The window identification
index addresses a color model table which determines the description of pixel data. For
example, separate windows displaying 24-plane true color, 8-plane pseudo color, and
24-plane double-buffer true color can exist within a single frame.
A programmable setup (0 or 7.5 IRE) is included.
Functional Block Diagram
CLOCK
CLOCK*
LD
SC*
P[127:0]
STSCAN
FIELD
SCEN*
Pixel Port
Registers
Clock
MPX
Pixel
Clock
PLL
Window
Lookup
Logic
Bus Control
R/W
Data Bus Mux
IOB
IOG
IOR
COMP
COMP2
Color
Model
Selection
VAA
1K x 8 RAM
3 x 8 Cursor LUT
1K x 8 RAM
3 x 8 Cursor LUT
1K x 8 RAM
3 x 8 Cursor LUT
Pixel Load
Control
Video
Timing
Generator
JT
A
G
TDO
TDI
TCK
TMS
64 x 64 x 2
Cursor RAM
Pipelines
CSYNC*,
VSYNC*
General
Purpose
PLL
GPCLK
DRAWING*
D[7:0]
LB*
C[1,0]
CE*
FSADJ
VREF
XTAL[2]
XTAL[1]
GND
497-8_001
Distinguishing Features
PLL pixel clock generation (M/N)
Supports true-color 1920 x 1200
resolutions
Up to 128-bit input pixel port width
240 and 160 MHz operation
Multiple display modes on a pixel
basis
High-resolution true-color support
2:1 and 4:1 multiplexed pixel port
support
Programmable pixel format
Three 1K x 8 color palette RAMs
64 x 64 x 2 programmable cursor
Programmable setup (0 or 7.5 IRE)
VRAM shift clock generation
On-chip user-definable video timing
generator
JTAG support
160-pin (Bt497A), 208-pin (Bt498A)
PQFP packages
LVTTL (3.3 V) I/O interface
Applications
High-resolution color 3D graphics
CAE/CAD/CAM
Image processing
Instrumentation
Desktop publishing
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