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参数资料
| 型号： | BU-61580S3-112K |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封装： | 48.30 X 25.40 MM, 4.19 MM HEIGHT, DIP-70 |
| 文件页数： | 25/44页 |
| 文件大小： | 563K |
| 代理商： | BU-61580S3-112K |
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31
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
H1 web-09/02-0
ns
0
STRBD valid high hold time from READYD rising edge
t18
note 6
ns
30
STRBD rising edge delay to IOEN rising edge and READYD rising edge
t17
ns
∞
READYD falling to STRBD rising edge release time
t16
note 6
ns
35
CLOCK IN rising edge delay to READYD falling
t15
note 2
ns
0
SELECT hold time following IOEN falling
t7
ns
50
Address valid setup time following SELECT and STRBD low (@ 12 MHz)
t4
notes 2, 6
ns
128.3
SELECT and STRBD low delay to IOEN low (uncontended access @ 12 MHz)
t2
notes 7, 8, 9
ns
30
Address valid setup time prior to CLOCK IN rising edge
t10
ns
10
Input Data valid setup time prior to CLOCK IN rising edge
t11
notes 9, 10
ns
30
Input Data valid hold time following CLOCK IN rising edge
t13
notes 7, 8, 9, 10
ns
30
Address valid hold time following to CLOCK IN rising edge
t12
notes 3, 4, 5, 7
ns
30
MEM/REG, RD/WR hold time prior to CLOCK IN falling edge
t9
notes 6, 10
ns
265
205
250
187.5
235
170
IOEN falling delay to READYD falling (@ 16 MHz)
t14
notes 3, 4, 5, 7
ns
10
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
t8
note 6
ns
35
70
50
CLOCK IN rising edge delay to IOEN falling edge
Input Data valid setup time following SELECT and STRBD low (@ 12 MHz)
Input Data valid setup time following SELECT and STRBD low (@ 16 MHz)
t6
t5
ns
30
Address valid setup time following SELECT and STRBD low (@ 16 MHz)
t4
notes 3, 4, 5, 7
ns
20
MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 12 MHz)
t3
notes 3, 4, 5, 7
ns
10
MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 16 MHz)
t3
notes 2, 6
s
2.8
SELECT and STRBD low delay to IOEN low (contended access @ 16 MHz)
t2
notes 2, 6
ns
107.5
SELECT and STRBD low delay to IOEN low (uncontended access @ 16 MHz)
t2
notes 2, 10
ns
10
SELECT and STRBD low setup time prior to CLOCK IN rising edge
t1
NOTE REFERENCE
UNITS
MAX
TYP
MIN
DESCRIPTION
REF
s
3.7
SELECT and STRBD low delay to IOEN low (contended access @ 12 MHz)
t2
TABLE FOR FIGURE 16. CPU WRITING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf
load. For loading above 50 pf, the validity of IOEN, READYD, and
D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. Timing for A15-A0, MEM/REG and SELECT assumes ADDR-LAT
is connected to logic "1." Refer to Address Latch timing for addition-
al details.
8. Internal RAM is accessed by A11 through A0 (A13 through A0 for
61585 and 61586). Registers are accessed by A4 through A0.
9. The address bus A15-A0 is internally buffered transparently until
the first rising edge of CLK after IOEN goes low. After this CLK
edge, A15-A0 become latched internally.
10. Setup time given for use in worst case timing calculations.
None of the ACE input signals are required to be synchronized to
the system clock. For ACE applications only, where SELECT and
STRBD do not meet the setup time of t1, but occur during the setup
window of an internal flip-flop, an additional clock cycle will be
inserted between the falling clock edge that latches MEM/REG and
RD/WR and the rising clock edge that latches the Address (A15-A0)
and data (D15-D0). When this occurs, the pulse width of IOEN
falling to READYD falling (t14) increases by one clock cycle and the
address hold time (t12 + t13) must be increased be one clock cycle.
Notes for FIGURE 16 and associated table.
1. For the 16-bit buffered nonzero wait configuration, TRANSPA-
RENT/BUFFERED must be connected to logic "0". ZERO_WAIT
and DTREQ/16/8 must be connected to logic "1". The inputs TRIG-
GER_SEL and MSB/LSB may be connected to either +5 V or
ground.
2. SELECT and STRBD may be tied together. IOEN goes low on
the first rising CLK edge when SELECT
STRBD is sampled low
(satisfying t1) and the BU-65170/61580's protocol/memory manage-
ment logic is not accessing the internal RAM. When this occurs,
IOEN goes low, starting the transfer cycle. After IOEN goes low,
SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for
register access.
4. MEM/REG and RD/WR are buffered transparently until the first
falling edge of CLK after IOEN goes low. After this CLK edge,
MEM/REG and RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLAR-
ITY_SEL is connected to logic "1." If POLARITY_SEL is connected
to logic "0," RD/WR must be asserted high to write.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BU-61580S3-122 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580S6-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580S6-110 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580S6-120 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580S6-200 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
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