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| 型号： | BU-62743B3-110L |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| 封装： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128 |
| 文件页数： | 71/93页 |
| 文件大小： | 504K |
| 代理商： | BU-62743B3-110L |
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Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
73
Table 58. CPU Reading Ram or Registers (Shown for 16-Bit, Buffered, Nonzero Wait Mode)
3.3V LOGIC
REF
DESCRIPTION
MIN TYP MAX
UNIT
t1
SELECT* and STRBD* low setup time prior to clock rising edge
(Notes 2,9)
15
ns
t2
SELECT* and STRBD* low to IOEN* low (uncontended access
@20 MHz) (Notes 2,6)
105
ns
(contended access, with ENHANCED CPU ACCESS
= “0”, @20 MHz) (Notes 2,6)
2.2
s
(contended access, with ENHANCED CPU ACCESS
= “1”, @20 MHz) (Notes 2,6)
355
ns
(uncontended access @16 MHz) (Notes 2,6)
117
ns
(contended access, with ENHANCED CPU ACCESS
= “0”, @16 MHz) (Notes 2,6)
2.8
s
(contended access, with ENHANCED CPU ACCESS
= “1”, @16 MHz) (Notes 2,6)
430
ns
(uncontended @12 MHz) (Notes 2,6)
138
ns
(contended access, with ENHANCED CPU ACCESS
= “0”, @12 MHz) (Notes 2,6)
3.7
s
(contended access, with ENHANCED CPU ACCESS
= “1”, @12 MHz) (Notes 2,6)
555
ns
(uncontended access @10 MHz) (Notes 2,6)
155
ns
(contended access, with ENHANCED CPU ACCESS
= “0”, @10 MHz) (Notes 2,6)
4.4
s
(contended access, with ENHANCED CPU ACCESS
= “1”, @10 MHz) (Notes 2,6)
655
ns
t3
Time for MEM/REG* and RD/WR* to become valid following
SELECT* and STRBD* low (@20 MHz) (Notes 3,4,5,7)
10
ns
@16 MHz (Notes 3,4,5,7)
16
ns
@12 MHz (Notes 3,4,5,7)
27
ns
@10 MHz (Notes 3,4,5,7)
35
ns
t4
Time for address to become valid following SELECT* and STRBD*
low (@20 MHz)
12
ns
@16 MHz
25
ns
@12 MHz
45
ns
@10 MHz
62
ns
t5
CLOCK IN rising edge delay to IOEN* falling edge (Note 6)
40
ns
t6
SELECT* hold time following IOEN* falling (Note 2)
0
ns
t7
MEM/REG*, RD/WR* setup time prior to CLOCK IN falling edge
(Notes 3,4,5,7)
15
ns
t8
MEM/REG*, RD/WR* hold time following CLOCK IN falling edge
(Notes 3,4,5,7)
30
ns
t9
Address valid setup time prior to CLOCK IN rising edge (Notes 7,8,)
35
ns
t10 Address hold time following CLOCK IN rising edge (Notes 7,8,9)
30
ns
t11 IOEN* falling delay to READYD* falling @20 MHz (Notes 6,9)
135
150
165
ns
@16 MHz (Notes 6,9)
170 187.5
205
ns
@12 MHz (Notes 6,9)
235
250
265
ns
@10 MHz (Notes 6,9)
270
300
315
ns
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