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参数资料
| 型号： | BU-63825D0-301 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封装： | CERAMIC, DIP-70 |
| 文件页数： | 24/48页 |
| 文件大小： | 405K |
| 代理商： | BU-63825D0-301 |
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30
Data Device Corporation
www.ddc-web.com
BU-63825
C-02/06-0
HOST
SP'ACE II
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
RTAD4-RTAD0
RT
ADDRESS,
PARITY
RTADP
D15-D8
+5V
-12V/-15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
POLARITY_SEL
(NOTE 3)
ZERO_WAIT
(NOTE 4)
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
CPU ACKNOWLEDGE
(NOTE 6)
RESET
NOTES:
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT
BYTE TRANSFER READ ACCESSES AND BY THE
LEAST SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES.
IF TRIGGER_SEL = "0", THEN INTERNAL 16-BIT
TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT
BYTE TRANSFER FOR READ ACCESSES AND BY THE MOST
SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES.
FOR ZERO WAIT INTERFACE (ZERO WAIT = "0"):
IF TRIGGER_SEL = "1", THEN INTERNAL 16-BIT
TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT
BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES.
IF TRIGGER_SEL = "0", THEN INTERNAL 16-BIT
TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT
BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES.
6. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO
WAIT TYPE OF INTERFACE.
1. CPU D7-D0 CONNECTS TO BOTH D15-D8 AND
D7-D0.
2. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS
WITH MULTIPLEXED ADDRESS/DATA BUFFERS.
3. IF POLARITY_SEL = "1", THEN MSB/LSB SELECTS THE MOST
SIGNIFICANT BYTE WHEN LOW, AND THE LEAST
SIGNIFICANT BYTE WHEN HIGH.
IF POLARITY_SEL = "0", THEN MSB/LSB SELECTS THE LEAST
SIGNIFICANT BYTE WHEN LOW, AND THE MOST
SIGNIFICANT BYTE WHEN HIGH.
4. ZERO WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR
NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR
ZERO WAIT INTERFACE.
5. OPERATION OF TRIGGER_SELECT INPUT IS AS FOLLOWS:
FOR NON-ZERO WAIT INTERFACE (ZERO WAIT = "1"):
IF TRIGGER_SEL = "1", THEN INTERNAL 16-BIT
A15-A14
A13-A0
N/C
ADDR_LAT
CPU ADDRESS LATCH
(NOTE 1)
16/8_BIT
TRANSPARENT/BUFFERED
+5V
CPU D7-D0
(NOTE 2)
A14-A1
CPU A14-A0
MSB/LSB
CPU A0
TRIGGER_SEL
(NOTE 5)
D7-D0
FIGURE 14. 8-BIT BUFFERED MODE
相关PDF资料 |
PDF描述 |
|---|---|
| BU-63825D1-191 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-63825D1-200 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-63825D1-201 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-63825D2-190 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-63825D2-200 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
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