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参数资料
| 型号： | BU-63825D2-190 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封装： | CERAMIC, DIP-70 |
| 文件页数： | 27/48页 |
| 文件大小： | 405K |
| 代理商： | BU-63825D2-190 |
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33
Data Device Corporation
www.ddc-web.com
BU-63825
C-02/06-0
ns
0
STRBD high hold time from READYD rising
t18
ns
50
CLOCK_IN rising edge delay to output data valid
t19
ns
40
STRBD rising delay to output Data tri-state
t17
ns
0
Output Data hold time following STRBD rising edge
t16
note 6
ns
40
STRBD rising edge delay to IOEN rising edge and READYD rising edge
t15
ns
∞
READYD falling to STRBD rising release time
t14
note 6
ns
30
CLOCK IN rising edge delay to READYD falling
t13
note 2
ns
0
SELECT hold time following IOEN falling
t6
ns
150
Address valid setup time following STRBD low (@ 12 MHz)
t4
notes 2, 6
ns
211.6
STRBD low delay to IOEN low (uncontended access @ 12 MHz)
t2
ns
10
Address valid setup time prior to CLOCK IN rising edge
t9
note 6
ns
455
437.5
420
IOEN falling delay to READYD falling (reading RAM @ 16 MHz)
t11
note 6
ns
205
187.5
170
IOEN falling delay to READYD falling (reading registers @ 16 MHz)
t11
note 6
ns
600
583.3
565
IOEN falling delay to READYD falling (reading RAM @ 12 MHz)
t11
notes 3, 4, 5
ns
25
MEM/REG, RD/WR hold time prior to CLOCK IN falling edge
t8
note 6
ns
54
Output Data valid prior to READYD falling (@ 12 MHz)
t12
note 6
ns
33
Output Data valid prior to READYD falling (@ 16 MHz)
t12
note 6
ns
265
250
230
IOEN falling delay to READYD falling (reading registers @ 12 MHz)
t11
note 9
ns
25
Address hold time following CLOCK IN rising edge
t10
notes 3, 4, 5
ns
10
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
t7
ns
30
CLOCK IN rising edge delay to IOEN falling edge
t5
ns
110
Address valid setup time following STRBD low (@ 16 MHz)
t4
ns
100
MEM/REG, RD/WR setup time following STRBD low(@ 12 MHz)
t3
ns
70
MEM/REG, RD/WR setup time following STRBD low(@ 16 MHz)
t3
notes 2, 6
s
5.3
STRBD low delay to IOEN low (contended access @ 16 MHz)
t2
notes 2, 6
ns
170
STRBD low delay to IOEN low (uncontended access @ 16 MHz)
t2
note 2
ns
15
SELECT and STRBD low setup time prior to clock rising edge
t1
NOTE REFERENCE
UNITS
MAX
TYP
MIN
DESCRIPTION
REF
s
7.05
STRBD low delay to IOEN low (contended access @ 12 MHz)
t2
TABLE FOR FIGURE 16. CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
Notes for FIGURE 16 and associated table.
1. For the 16-bit buffered configuration, the inputs TRIGGER_SEL and
MSB/LSB may be connected to +5 V or GND. For the nonzero wait
interface ZEROWAIT, must be connected to logic “1”.
2. SELECT and STRBD may be tied together. IOEN goes low on the
second rising CLK edge when STRBD is sampled low, provided
SELECT is also sampled low on that CLK edge and the BU-
63825/925’s protocol/memory management logic is not accessing
internal RAM. If the protocol/memory management logic is access-
ing internal RAM, SELECT is latched on the second rising CLK
edge and transfer will begin once protocol/memory management
access is complete. If SELECT is sampled high on the second ris-
ing CLK edge, no transfer will take place. IOEN will not drop.
3. MEM/REG must be presented high for memory access, low for
register access.
4. MEM/REG and RD/WR are buffered transparently until the first
falling edge of CLK after IOEN goes low. After this CLK edge,
MEM/REG and RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLARI-
TY_SEL is connected to logic "1". If POLARITY_SEL is connected
to logic "0", RD/WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load.
For loading above 50 pf, the validity of IOEN, READYD, and D15-
D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. Timing for A15-A0 assumes ADDR-LAT is connected to logic “1”.
Refer to Address Latch timing for additional details.
8. Internal RAM is accessed by A13 through A0. Registers are
accessed by A4 through A0.
9. The address bus A15-A0 is internally buffered transparently until
the first rising edge of CLK after IOEN, goes low. After this CLK
edge, A15-A0 become latched internally.
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