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参数资料
| 型号： | BU-63925G3-190 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| 封装： | CERAMIC, GULL LEAD, 70 PIN |
| 文件页数： | 6/48页 |
| 文件大小： | 405K |
| 代理商： | BU-63925G3-190 |
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14
Data Device Corporation
www.ddc-web.com
BU-63825
C-02/06-0
BC MEMORY MANAGEMENT
FIGURE 3 illustrates the BU-63825’s BC memory management
scheme. One of the BC memory management features is the
global double buffering mechanism. This provides for two sets of
the various BC mode data structures: Stack Pointer and
Message Counter locations, Descriptor Stack areas, and BC
message blocks. Bit 13 of Configuration Register #1 selects the
current active area. At any point in time, the BU-63825’s internal
1553 memory management logic may access only the various
data structures within the “active” area. FIGURE 3 delineates the
“active” and “inactive” areas by the nonshaded and shaded
areas, respectively; however, at any point in time, both the
“active” and “nonactive” areas are accessible by the host proces-
sor. In most applications, the host processor will access the “non-
active” area, while the 1553 bus processes the “active” area mes-
sages.
The BC may be programmed to transmit multimessage frames of
up to 512 messages. The number of messages to be processed
is programmable by the Active Area Message Count location in
the shared RAM, initialized by the host processor. In addition, the
host processor must initialize another location, the Active Area
Stack Pointer. The Stack Pointer references the four-word mes-
sage block descriptor in the Stack area of shared RAM for each
message to be processed. The BC Stack size is programmable
with choices of 256, 512, 1024, and 2048 words.
In the BC Frame Auto-Repeat mode, the Initial Stack Pointer and
Initial Message Counter locations must be loaded by the host
prior to the processing of the first frame. The single frame mode
does not use these two locations
The third and fourth words of the BC block descriptor are the
Intermessage Gap Time and the Message Block Address for the
respective message. These two memory locations must be writ-
ten by the host processor prior to the start of message process-
ing. Use of the Intermessage Gap Time is optional. The Block
Address pointer specifies the starting location for each message
block. The first word of each BC message block is the BC Control
Word.
At the start and end of each message, the Block Status and Time
Tag Words write to the message block descriptor in the stack.
The Block Status Word includes indications of message in
process or message completion, bus channel, Status Set,
response timeout, retry count, Status address mismatch, loop
test (on-line self-test) failure, and other error conditions. TABLE
23 illustrates the bit mapping of the BC Block Status word. The
16-bit Time Tag Word will reflect the current contents of the inter-
nal Time Tag Register. This read/writable register, which oper-
ates for all three modes, has programmable resolution of from 2
to 64 s/LSB. In addition, the Time Tag register may be clocked
from an external source.
15
13
0
CURRENT
AREA B/A
CONFIGURATION
REGISTER 1
INITIAL STACK
POINTERS (NOTE)
INITIAL MESSAGE
COUNTERS
MESSAGE
COUNTERS
STACK
POINTERS
BLOCK STATUS WORD
TIME TAG WORD
MESSAGE
GAP TIME WORD
MESSAGE
BLOCK ADDR
DESCRIPTOR
STACKS
MESSAGE
BLOCKS
MESSAGE
BLOCK
MESSAGE
BLOCK
FIGURE 3. BC MODE MEMORY MANAGEMENT
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