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参数资料
| 型号： | BU-64703B9-300 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80 |
| 封装： | CERAMIC, BGA-80 |
| 文件页数： | 13/48页 |
| 文件大小： | 405K |
| 代理商： | BU-64703B9-300 |
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20
Data Device Corporation
www.ddc-web.com
BU-64703
D-03/06-0
t1
CLOCK IN rising to DTREQ low
ALL
ns
t2
DTREQ (low) - to - DTGRT (low) delay time
ALL
s
t4
DTGRT low setup prior to CLOCK IN rising
ALL
ns
t6
CLOCK IN rising to DTACK low
ALL
ns
t7
Data output valid following CLOCK IN rising
ALL
ns
t8
DTGRT hold time following DTACK falling
ALL
ns
t10
Data output setup time prior to MEMWR low
t12
MEMWR low pulse width
t13
CLOCK IN rising to MEMWR high
ALL
ns
t15
CLOCK IN rising to DTREQ and DTACK high
ALL
ns
REF
DESCRIPTION
CLOCK
FREQUENCY
UNITS
TABLE FOR FIGURE 11. SSRT Mark3 DMA WRITE TIMING (NON-BURST)
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t3
CWC setup time prior to MEMWR falling
(see Note)
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t5
DTGRT falling to DTACK low
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t9
DTACK low pulse width
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t11
CLOCK IN rising to MEMWR low
ALL
ns
t14
Data output hold time following MEMWR high
20 MHz
ns
16 MHz
ns
12 MHz
ns
10 MHz
ns
t17
Data output signal Tri-State following CLOCK IN rising
ALL
ns
15
VALUE @3.3 VOLTS
MIN
TYP
MAX
40
10
40
30
40
60
85
127
160
40
50
52.5
62.5
73.3
83.3
90
100
110
148
210
260
105
118
138
155
200
250
333
400
40
10
23
43
60
40
t16
Data output hold time following CLOCK IN rising
ALL
ns
15
(1)
Assumes that DTGRT is low at the time DTREQ is asserted low. If not, these values can increase by the delay time from DTREQ (low) - to - DTGRT (low).
FIGURE 11. DMA WRITE TRANSFER (NON-BURST-MODE) TIMING
CLOCK IN
DTREQ
DTGRT
DTACK
MEMWR
MEMOE
WC/MC/CWC
D15-D0
DATA
VALID
t1
t2
t6
t5
t4
t8
t11
t12
t13
t17
t16
t7
t14
t10
t3
t15
L-BRO, T/R,
SA4-SA0
VALID
CWC = 0
t9
NON-BURST DMA WRITE
NOTE: With the DTGRT pin tied to GND, the time from DTREQ to DTACK is 1 clock cycle.
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