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参数资料
| 型号： | BU-65527C4-300 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), MIL-STD-1553 CONTROLLER, XMA |
| 文件页数： | 1/32页 |
| 文件大小： | 2094K |
| 代理商： | BU-65527C4-300 |
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DESCRIPTION
The BU-65528 and BU-65527 pro-
vide
full,
intelligent
interfacing
between
multiple
dual-redundant
MIL-STD-1553A/B Notice 2 Data
Buses and parallel VMEbus and
VXIbus. Software controls the opera-
tion of each independent channel of
the BU-65528 as either a MIL-STD-
1553 Bus Controller (BC), Remote
Terminal
(RT),
or
Bus
Monitor
Terminal (MT). The BU-65527M is a
militarized version of the BU-65528M
card which is conduction-cooled as
per IEEE 1101.2.
The BU-65527C
card is similar to the BU-65528 card
except it is air-cooled and contains no
wedge locks.
In addition, the BU-
65527C and BU-65527M access the
1553 bus through the standard P2
connector (refer to the mechanical
outline figures for details).
The BU-65528 and BU-65527 imple-
ment each dual-redundant 1553 inter-
face through the use of DDC's BU-
61586
and
BU-61585
Advanced
Communication Engine (ACE) com-
ponents, respectively.
The BU-65528 /27 may be configured
with one, two, three, or four ACE com-
ponents, providing an option to inter-
face with up to four independent 1553
buses using a single double eurocard
(VXI B size card).
Each 1553 channel contains 12K x 16
of on-board RAM. The shared RAM is
fully double buffered, preventing par-
tially updated data from being read by
the VME/VXI host or transmitted to
the 1553 data bus.
Each mode of operation (BC, RT, and
MT) implements sophisticated data
buffering structures which reduce the
real-time software requirements and
off-load the host processor.
The BC mode's frame auto-repeat
option and programmable intermes-
sage gap time provide a simple mech-
anism for controlling the repetitive tim-
ing of 1553 messages. Other BC fea-
tures include automatic retries, flexi-
ble support of 1553A devices, and
programmable response timeout.
MIL-STD-1553B BC/RT/MT
VME/VXI INTERFACE UNIT
FEATURES
VMEbus/VXIbus Interface
Multiprotocol Support of MIL-STD-
1553A and B Notice 2.
Commercial and Militarized
Versions Available
Programmable BC Gap Times
BC Frame Auto-Repeat
Automatic BC Retries
Flexible RT Data Buffering
Selective Message Monitor
Simultaneous RT/Monitor Mode
12K x 16 Shared RAM
Flexible Interrupt Generation
Comprehensive Self-Test
Capability
BU-61585
or
BU-61586
ACE
BC/RT/MT
DATA
CONTROL LOGIC,
ADDRESS DECODING,
ID REGISTER,
STATUS/CONTROL
REGISTER,
OFFSET REGISTER,
VECTOR/LEVEL
REGISTER
ADDRESS
BUFFER
D15-D1
A15-A1
DS0
DS1
AS
IRQ7-IRQ1
IACK
IACK IN
IACK OUT
DTACK
RD/WR
SYS RESET
MOD ID
AM5-AM0
VME
or
VXI
BUS
Channel #1
Ch. #2
Ch. #3
Ch. #4
1999, 1995 Data Device Corporation
FIGURE 1. BU-65528 AND BU-65527 BLOCK DIAGRAM
BU-65528
BU-65527M
BU-65528 and BU-65527
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