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◎
BU2288FV(VDD=3.3V, Ta=25℃, Crystal frequency 27.0000MHz, unless otherwise specified.)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Output L voltage
VOH
2.4
-
V
IOH=-4.0mA
Output H voltage
VOL
-
0.4
V
IOL=4.0mA
FSEL input VthL
VthL
0.2VDD
-
V
*4
FSEL input VthH
VthH
-
0.8VDD
V
*4
Hysteresis range
Vhys
0.2
-
V
Vhys=VthH-VthL*4
Action circuit current
IDD
-
27.0000
40.5
mA
At no load
CLK512-44
-
22.5792
-
MHz
At FSEL1=OPEN XTAL*3136/625/6
CLK512FS
CLK512-48
-
24.5760
-
MHz
At FSEL1=L XTAL*2048/375/6
CLK33M
-
33.8688
-
MHz
XTAL*3136/625/4
CLK16M
-
16.9344
-
MHz
XTAL*3136/625/8
CLK27M
-
27.0000
-
MHz
XTAL direct out
CLKA-A
-
16.9344
-
MHz
At FSEL1=OPEN XTAL*3136/625/8
CLK A
CLKA-B
-
36.8640
-
MHz
At FSEL1=L XTAL*2048/375/4
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ
P-J 1σ
-
70
-
psec
*1
Period-Jitter
MIN-MAX
P-J
MIN-MAX
-
420
-
psec
*2
Rise time
Tr
-
2.5
-
nsec
Period of transition time required for the
output reach 80% from 20% of VDD.
Fall time
Tf
-
2.5
-
nsec
Period of transition time required for the
output reach 20% from 80% of VDD.
Output Lock-Time
Tlock
-
1
msec
*
3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
◎
BU2360FV(VDD=3.3V, Ta=25℃, Crystal frequency 27.0000MHz, unless otherwise specified.)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Output L voltage
VOL
-
0.4
V
IOL=4.0mA
Output H voltage
VOH
2.4
-
V
IOH=-4.0mA
FSEL input VthL
VthL
0.2VDD
-
V
*4
FSEL input VthH
VthH
-
0.8VDD
V
*4
Hysteresis range
Vhys
0.2
-
V
Vhys = VthH - VthL *4
Action circuit current
IDD
-
27.0
40.5
mA
At no load
CLK27M
-
27.0000
-
MHz
XTAL direct out
CLK33M
-
33.8688
-
MHz
XTAL×3136 / 625 / 4
CLK512_48
-
24.5760
-
MHz
At FSEL=H, XTAL×2048 / 375 / 6
CLK512FS
CLK512_44
-
22.5792
-
MHz
At FSEL=L, XTAL×3136 / 625 / 6
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ
P-J 1σ
-
70
-
psec
*1
Period-Jitter
MIN-MAX
P-J
MIN-MAX
-
420
-
psec
*2
Rise Time
Tr
-
2.5
-
nsec
Period of transition time required for the
output reach 80% from 20% of VDD.
Fall Time
Tf
-
2.5
-
nsec
Period of transition time required for the
output reach 20% from 80% of VDD.
Output Lock-Time
Tlock
-
1
msec
*3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.