参数资料
| 型号： | BU2506FV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT 8-CHAN SSOP20 |
| 标准包装： | 1 |
| 设置时间： | 7µs |
| 位数： | 10 |
| 数据接口： | 串行 |
| 转换器数目： | 8 |
| 电压电源： | 单电源 |
| 工作温度： | -30°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-LSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-SSOP-B |
| 包装： | 标准包装 |
| 输出数目和类型： | 8 电压，单极 |
| 采样率（每秒）： | * |
| 产品目录页面： | 1376 (CN2011-ZH PDF) |
| 其它名称： | BU2506FV-E2DKR |
BU2506FV,BU2505FV
Technical Note
4/10
www.rohm.com
2011.04 - Rev.B
2011ROHM Co., Ltd. All rights reserved.
●
Cascade Connection
A data output terminal for cascade connection (DO) is available for reducing the number of parts when it is increased.
The DO terminal can be connected to a data input terminal (DI) of the next IC.
However, DO transition is synchronized with rising edge of clock signal, DO signal should be delayed, to keep a limit of data hold
time.
For example RC passive filter can be used.
Also in some cases, an operation frequency of logic signal have to be decreased to ensure a margin of data setup time.
Therefore, it is better to control LD port of each LSI separately, if extra CPU ports are available.
In this case, more ports to control LD signals are needed, but a consideration described above doesn’t have do be done.
BU2505FV
BU2506FV
(#2)
BU2505FV
BU2506FV
(#1)
LD
CLK
DI
LD
CLK
DI
LD1
LD2
DI
CLK
BU2505FV
BU2506FV
DO
LD
CLK
DI
(#2)
BU2505FV
BU2506FV
DO
LD
CLK
DI
(#1)
CPU
LD
CLK
DI
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BU2506-M3/45 | 制造商:Vishay Semiconductors 功能描述:25A,600V,STD,INLINE POWER BRIDGE |
| BU2506-M3/51 | 制造商:Vishay Semiconductors 功能描述:25A,600V,STD,INLINE POWER BRIDGE |
| BU2507 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Silicon Diffused Power Transistor |
| BU2507AF | 制造商:ISC 制造商全称:Inchange Semiconductor Company Limited 功能描述:isc Silicon NPN Power Transistor |
| BU2507AX | 制造商:ISC 制造商全称:Inchange Semiconductor Company Limited 功能描述:isc Silicon NPN Power Transistor |
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