参数资料
型号: BU7232F-E2
厂商: Rohm Semiconductor
文件页数: 4/19页
文件大小: 0K
描述: IC COMPARATOR DUAL 5.5V SOP-8
标准包装: 1
类型: 通用
元件数: 2
输出类型: 推挽式
电压 - 电源,单路/双路(±): 1.8 V ~ 5.5 V,±0.9 V ~ 2.75 V
电压 - 输入偏移(最小值): 11mV @ 3V
电流 - 输入偏压(最小值): 1pA @ 3V
电流 - 输出(标准): 6mA @ 3V
电流 - 静态(最大值): 25µA
CMRR, PSRR(标准): 80dB CMRR,80dB PSRR
传输延迟(最大): 1.7µs
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.173",4.40mm 宽)
安装类型: 表面贴装
包装: 标准包装
产品目录页面: 1377 (CN2011-ZH PDF)
其它名称: BU7232F-E2DKR
IDT / ICS 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER
12
ICS8430B-71 REV A NOVEMBER 20, 2006
ICS8430B-71
700MHZ, CRYSTAL INTERFACE/LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as
possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the
power (ground) plane and the component power (ground) pins.
If V
CCA
shares the same power supply with V
CC
, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as
close to the V
CCA
as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than
other signals. Any ringing on the rising or falling edge or
excessive ring back can cause system failure. The trace shape
and the trace delay might be restricted by the available space
on the board and the component location. While routing the
traces, the clock signal traces should be routed first and should
be locked prior to routing other signal traces.
The traces with 50
transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and run
adjacent to each other. Avoid sharp angles on the clock
trace. Shar p angle tur ns cause the character istic
impedance to change on the transmission lines.
Keep the clock trace on the same layer. Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow more space between the clock trace
and the other signal trace.
Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in
this example.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length
between the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other signal
traces should not be routed near the crystal traces.
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8430B-71
TL1N
C14
R1
TL1, TL21N are 50 Ohm
traces and equal length
TL1
C1
Close to the input
pins of the
receiver
GND
TL1N
C2
VCC
R7
PIN 1
X1
R3
VIA
VCCA
C11
C15
C16
R4
TL1
U1
R2
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