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参数资料
| 型号： | BU7325HFV-TR |
| 元件分类： | XO, clock |
| 英文描述： | 78 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 封装： | ROHS COMPLIANT, HVSOF-6 |
| 文件页数： | 12/21页 |
| 文件大小： | 1528K |
| 代理商： | BU7325HFV-TR |
2/20
●
Recommended Operating Range
Parameter
Symbol
Limit
Unit
Supply voltage
VDD
3.0～3.6
Ｖ
Input H voltage
VINH
0.8VDD～VDD
Ｖ
Input L voltage
VINL
0.0～0.2VDD
Ｖ
Operating temperature
Topr
-5～70
℃
Output load
CL
15(MAX)
pF
●
Electrical characteristics
BU3071HFV（Ta=25℃, VDD=3.3V,Crystal frequency=28.6363MHz, unless otherwise specified.）
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Output H voltage
VOH
2.8
-
V
IOH=-4.0mA
Output L voltage
VOL
-
0.5
V
IOL=4.0mA
Consumption current 1
IDD1
-
10
15
mA
OE=H, at no load
Consumption current 2
IDD2
-
1
1.3
mA
OE=L
Output frequency
-
54.0000
-
MHz
IN*264/35/4
The following parameters represent design guaranteed performance.
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ
PJsSD
-
50
-
psec
※
1
Period-Jitter MIN-MAX
PJsABS
-
300
-
psec
※
2
Rise time
tr
-
2.5
-
nsec
Period of transition time required for the
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Fall time
tf
-
2.5
-
nsec
Period of transition time required for the
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time
tLOCK
-
1
msec
※
3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.If the input
frequency is set to 28.6363MHz, the output frequency will be as listed above.
BU3072HFV（Ta=25℃, VDD=3.3V, Crystal frequency=48.0000MHz, unless otherwise specified.）
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Output H voltage
VOH
2.8
-
V
IOH=-4.0mA
Output L voltage
VOL
-
0.5
V
IOL=4.0mA
Consumption current 1
IDD1
-
11
16
mA
PD=H, at no load
Consumption current 2
IDD2
-
5
μ
A
PD=L
CLK_27
-
27.0000
-
MHz
SEL=L, IN*18/8/4
Output frequency
CLK_36
-
36.0000
-
MHz
SEL=H, IN*24/8/4
The following parameters represent design guaranteed performance.
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ
PJsSD
-
35
-
psec
※
1
Long-Term-Jitter
MIN-MAX
LTJsABS
-
0.9
1.5
nsec
MIN-MAX of long-term jitter (100
sec
from trigger)
Rise time
tr
-
2.5
-
nsec
Period of transition time required for the
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Fall time
tf
-
2.5
-
nsec
Period of transition time required for the
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time
tLOCK
-
1
msec
※
3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.If the input
frequency is set to 48.0000MHz, the output frequency will be as listed above.
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