参数资料
| 型号： | BU9882F-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 2/21页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 400KHZ 14SOP |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K（128 x 8 x 2） |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOP |
| 包装： | 带卷 (TR) |
BR24C21xxx Series (1K)
● Recommended Operating Ratings
Datasheet
Parameter Symbol
Ratings
Unit
Supply Voltage
Input voltage
V CC
VIN
2.5 to 5.5
0 to Vcc
V
● Electrical characteristics
DC (Unless otherwise specified, Ta=-40 ℃ to +85 ℃? V CC =2.5V to 5.5V)
Parameter
“H” Input Voltage 1
“L” Input Voltage 1
“H” Input Voltage 2
“L” Input Voltage 2
“L” Input Voltage 3
“L” Output Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Symbol
VIH1
VIL1
VIH2
VIL2
VIL3
VOL
ILI
ILO
ICC
ISB
Min.
0.7V CC
-
2.0
-
-
-
-1
-1
-
-
Limits
Typ.
-
-
-
-
-
-
-
-
-
10
Max.
-
0.3V CC
-
0.8
0.2V CC
0.4
1
1
3.0
100
Unit
V
V
V
V
V
V
μA
μA
mA
μA
Condition
SCL, SDA
SCL, SDA
VCLK
VCLK, V CC ≧ 4.0V
VCLK, V CC ＜ 4.0V
SDA, IOL=3.0mA
SCL, VCLK, VIN=0V to V CC
SDA, VOUT=0V to V CC
V CC =5.5V, fSCL=400kHz
V CC =5.5V, SDA=SCL=V CC ,VCLK=GND *1
*1 Transmit-Only Mode - After power on, the BR24C21/F/FJ/FV is in Standby mode and does not provide the clock to the VCLK pin.
After the clock is provided to VCLK, the device is switched from Standby to Transmit-Only Mode, and the operating current flows.
Bi-directional Mode - The BR24C21/F/FJ/FV is in Standby mode after each command is performed.
AC (Unless otherwise specified, Ta=-40 ℃ to +85 ℃ ,V CC =2.5V to 5.5V)
Fast-mode
Standard-mode
Parameter
Symbol
V CC =2.5V to 5.5V
V CC =2.5V to 5.5V
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Clock Frequency
Data Clock High Period
Data Clock Low Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time(SCL)
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tSU:STO
tBUF
tWR
tI
-
0.6
1.3
-
-
0.6
0.6
0
100
-
0.6
1.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
0.3
0.3
-
-
-
-
0.9
-
-
10
0.1
-
4.0
4.7
-
-
4.0
4.7
0
250
0.2
4.0
4.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
-
-
1.0
0.3
-
-
-
-
3.5
-
-
10
0.1
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
ms
μs
AC OPERATING CHARACTERISTICS (Transmit-Only Mode)
Output Data Delay Time(VCLK)
VCLK High Period
VCLK Low Period
VCLK Setup Time
VCLK Hold Time
Mode Transition Time
Transmit-Only Powerup Time
Noise Spike Width (VCLK)
tVPD
tVHIGH
tVLOW
tVSU
tVHD
tVHZ
tVPU
tVI
-
0.6
1.3
0
0.6
-
0
-
-
-
-
-
-
-
-
-
1.0
-
-
-
-
0.5
-
0.1
-
4.0
4.7
0
4.0
-
0
-
-
-
-
-
-
-
-
-
2.0
-
-
-
-
1.0
-
0.1
μs
μs
μs
μs
μs
μs
μs
μs
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TSZ22111 ? 15 ? 001
2/18
TSZ02201-0R2R0G100270-1-2
10.Jul.2012 Rev.001
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