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参数资料
| 型号： | BX80526F500256E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 500 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | FCPGA2-370 |
| 文件页数： | 1/94页 |
| 文件大小： | 1014K |
| 代理商： | BX80526F500256E |
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Pentium III Processor for the PGA370
Socket at 500 MHz to 1.13 GHz
Datasheet
Revision 8
Product Features
The Pentium
III processor is designed for high-performance desktops and for workstations and
servers. It is binary compatible with previous Intel Architecture processors. The Pentium III processor
provides great performance for applications running on advanced operating systems such as Windows*
98, Windows NT and UNIX*. This is achieved by integrating the best attributes of Intel processors—
the dynamic execution, Dual Independent Bus architecture plus Intel MMX technology and Internet
Streaming SIMD Extentions— bringing a new level of performance for systems buyers. The Pentium
III processor is scaleable to two processors in a multiprocessor system and extends the power of the
Pentium
II processor with performance headroom for business media, communication and internet
capabilities. Systems based on Pentium III processors also include the latest features to simplify system
management and lower the cost of ownership for large and small business environments. The Pentium
III processor offers great performance for today’s and tomorrow’s applications.
FC-PGA370 Package
s
Available in 1.13 GHz, 1B GHz, 933, 866,
800EB, 733, 667, 600EB, and 533EB MHz
for a 133 MHz system bus
s
Available in 1.10 GHz, 1 GHz, 900, 850,
800, 750, 700, 650, 600E, 550E, and 500E
MHz for a 100 MHz system bus
s
System bus frequency at 100 MHz and
133 MHz (“E” denotes support for
Advanced Transfer Cache and Advanced
system buffering; “B” denotes support for a
133 MHz system bus where both bus
frequencies are available for order per each
given core frequency; See Table 1 for a
summary of features for each line item.)
s
Available in versions that incorporate
256-KB Advanced Transfer Cache (on-die,
full speed Level 2 (L2) cache with Error
Correcting Code (ECC))
s
Dual Independent Bus (DIB) architecture:
Separate dedicated external System Bus and
dedicated internal high-speed cache bus
s
Internet Streaming SIMD Extensions for
enhanced video, sound and 3D performance
s
Binary compatible with applications running
on previous members of the Intel
microprocessor line
s
Dynamic execution micro architecture
s
Intel Processor Serial Number
s
Power Management capabilities
— System Management mode
— Multiple low-power states
s
Optimized for 32-bit applications running on
advanced 32-bit operating systems
s
Flip Chip Pin Grid Array (FC-PGA/FC-PGA2)
packaging technology; FC-PGA/FC-PGA2
processors deliver high performance with
improved handling protection and socketability
s
Integrated high performance 16-KB instruction
and 16-KB data, nonblocking, level one cache
s
256-KB Integrated Full Speed level two cache
allows for low latency on read/store operations
s
Double Quad Word Wide (256 bit) cache data
bus provides extremely high throughput on
read/store operations.
s
8-way cache associativity provides improved
cache hit rate on reads/store operations.
s
Error-correcting code for System Bus data
s
Enables systems which are scaleable for up to
two processors
June 2001
Document Number: 245264-08
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相关代理商/技术参数 |
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|---|---|
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