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参数资料
| 型号： | BX80536GE1866FJ |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1860 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, MICRO PGA-478 |
| 文件页数： | 4/30页 |
| 文件大小： | 887K |
| 代理商： | BX80536GE1866FJ |
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12
Datasheet
Low Power Features
2.1.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven
(allowing the level to return to V
CCP) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the FSB should be driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be
deasserted ten or more bus clocks after the de-assertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
FSB (see Section 2.1.4). A transition to the Sleep state (see Section 2.1.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the processor, and
only serviced when the processor returns to the Normal State. Only one occurrence of each event
will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the FSB and it will latch interrupts
delivered on the FSB.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if
there is any pending interrupt latched within the processor. Pending interrupts that are blocked by
the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it should return the processor to the Normal state.
2.1.4
HALT/Grant Snoop State
The processor will respond to snoop or interrupt transactions on the FSB while in Stop-Grant state
or in AutoHALT Power Down state. During a snoop or interrupt transaction, the processor enters
the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the FSB has
been serviced (whether by the processor or another agent on the FSB) or the interrupt has been
latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-
Grant state or AutoHALT Power Down state, as appropriate.
2.1.5
Sleep State
The Sleep state is a low power state in which the processor maintains its context, maintains the
phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered
from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon
the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the
Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of
specification and may result in unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
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