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| 型号： | C161S |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位单片机 |
| 文件页数： | 9/75页 |
| 文件大小： | 1315K |
| 代理商： | C161S |
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C161S
General Device Information
Data Sheet
5
V1.0, 2003-11
Table 2
Symbol
Pin Definitions and Functions
Pin
No.
Outp.
2
I
XTAL1:
Input
Function
XTAL1
XTAL2
3
O
Input to the oscillator amplifier and input to the
internal clock generator
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics (see
Chapter 5.4
) must be observed.
Port 3 is a 12-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as
push/pull or open drain drivers.
The following Port 3 pins also serve for alternate functions:
CAPIN
GPT2 Register CAPREL Capture Input
T3OUT
GPT1 Timer T3 Toggle Latch Output
T3EUD
GPT1 Timer T3 External Up/Down Control Input
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp.
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp.
MRST
SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR
SSC Master-Transmit/Slave-Receive Outp./Inp.
TxD0
ASC0 Clock/Data Output (Async./Sync.)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
BHE
External Memory High Byte Enable Signal,
WRH
External Memory High Byte Write Strobe
SCLK
SSC Master Clock Output / Slave Clock Input.
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
Port 4 can be used to output the segment address lines:
A16
Least Significant Segment Address Line
A17
Segment Address Line
A18
Segment Address Line
A19
Segment Address Line
A20
Segment Address Line
A21
Segment Address Line
XTAL2:
P3
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P4
5
6
7
8
9
10
11
12
13
14
15
16
IO
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
IO
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
17
18
19
20
23
24
O
O
O
O
O
O
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