C165UTAH
Overview
Data Sheet
12
2001-02-23
– S/G access support
Four On-Chip Independent Full-Duplex HDLC Formatters
– 8 independent 8-byte FIFOs for each transmit and receive channel
USART Interface with AutoBaud Support (1,200 bit/s - 230,400 bit/s)
– AT-Command sensitive AutoBaud Detection
1.1
Key Features
The C165UTAH is a new low-cost member of the Infineon Communication Controller
family. The device has the following features:
C166 Static Core with Peripherals including:
– Full-static core up to 18 MIPS (@36 MHz)
– Peripheral Event Controller (PEC) for 8 independent DMA channels
– 16 Dynamically Programmable Priority-Level Interrupt System
– Eight External Interrupts
– Up to 72 SW-configurative Input/Output (I/O) Ports, some with Interrupt Capabilities
– 8-bit or 16-bit External Data Bus
– Multiplexed or Demultiplexed Address/Data Bus
– Up to 8-Mbyte Linear Address Space for Code and Data
– Five Programmable Chip-Select Lines with Wait-State Generator Logic
– On-Chip 3,072-Byte Dual-Port SRAM for user applications
– On-Chip 1,024-Byte Special Function Register Area
– On-Chip PLL with Output Clock Signal
– Five Multimode General Purpose Timers
– On-Chip Programmable Watchdog Timer
– Glueless Interface to EPROM, Flash EPROM and SRAM
– Low-Power Management Supporting Idle-, Power-Down- and Sleep-Mode and
additional CPU clock slow-down mode with mode control for each peripheral
– USART interface with Auto Baud Rate detection up to 230,400 kbit/s
– USART Baud Rate generation in asynchronous mode up to 2.25 MBaud @ 36 MHz
– USART Baud Rate generation in synchronous mode up to 4.5 MBaud @ 36 MHz
– USART standard Baud Rates generation with very small deviation (230.4 kBaud
< 0.01%, 460.8 kBaud < 0.15 %, 691.2 kBaud < 0.04 %, 921.6 kBaud < 0.15 % ) @
36 MHz
– High speed Serial Synchronous Channel Interface (SSC) with ALIS-3.0 and AC97
compatibility up to 18 MBaud in SSC Master Mode and up to 9 MBaud in SSC Slave
Mode @ 36 MHz