参数资料
型号: C8051F002-GQ
厂商: Silicon Laboratories Inc
文件页数: 17/171页
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 32LQFP
产品培训模块: Serial Communication Overview
标准包装: 250
系列: C8051F00x
核心处理器: 8051
芯体尺寸: 8-位
速度: 20MHz
连通性: SMBus(2 线/I²C),SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 8
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 4x12b; D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 32-LQFP
包装: 托盘
产品目录页面: 621 (CN2011-ZH PDF)
配用: 336-1246-ND - DEV KIT F300/301/302/303/304/305
其它名称: 336-1186
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16. SMBus / I2C Bus
The SMBus serial I/O interface is compliant with the System Management Bus Specification, version 1.1. It is a
two-wire, bi-directional serial bus, which is also compatible with the I
2C serial bus. Reads and writes to the
interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial
transfer of the data. Data can be transferred at up to 1/8
th of the system clock if desired (this can be faster than
allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low
duration is used to accommodate devices with different speed capabilities on the same bus.
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver, and
data transfers from an addressed slave transmitter to a master receiver. The master device initiates both types of
data transfers and provides the serial clock pulses. The SMBus interface may operate as a master or a slave.
Multiple master devices on the same bus are also supported. If two or more masters attempt to initiate a data
transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration.
Figure 16.1. SMBus Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write to
SMB0DAT
SMBUS CONTROL LOGIC
Read
SMB0DAT
SMB0ADR
S
L
V
6
G
C
S
L
V
5
S
L
V
4
S
L
V
3
S
L
V
2
S
L
V
1
S
L
V
0
C
R
O
S
B
A
R
Clock Divide
Logic
SYSCLK
SMB0CR
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
SCL
FILTER
N
SDA
Control
0000000b
7 MSBs
8
A
B
A=B
8
0
1
2
3
4
5
6
7
SMB0DAT
8
SMB0CN
S
T
A
S
I
A
F
T
E
T
O
E
N
S
M
B
U
S
Y
S
T
O
SMB0STA
S
T
A
4
S
T
A
3
S
T
A
2
S
T
A
1
S
T
A
0
SCL
Control
Status Generation
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
IRQ Generation
S
T
A
5
S
T
A
6
S
T
A
7
A
B
A=B
SMBUS
IRQ
Interrupt
Request
Port I/O
1
0
SDA
FILTER
N
7
113
Rev. 1.7
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