参数资料
型号: C8051F005-GQR
厂商: Silicon Laboratories Inc
文件页数: 69/171页
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 64TQFP TAP
产品培训模块: Serial Communication Overview
标准包装: 500
系列: C8051F00x
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 32
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x12b,D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 带卷 (TR)
配用: 336-1188-ND - DEV KIT FOR F005/006/007
其它名称: 977.000
Q2567667
Q2910019
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.3.
Register Descriptions for PCA
The system device may implement one or more Programmable Counter Arrays. Following are detailed descriptions
of the special function registers related to the operation of the PCA. The CIP-51 System Controller section of the
datasheet provides additional information on the SFRs and their use.
Figure 20.8. PCA0CN: PCA Control Register
R/W
Reset Value
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xD8
Bit7:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When
the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to
vector to the CF interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
Bit6:
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
Bit5:
UNUSED. Read = 0, Write = don’t care.
Bit4:
CCF4: PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit3:
CCF3: PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit2:
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit1:
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit0:
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Rev. 1.7
160
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