参数资料
型号: C8051F005DK-U
厂商: Silicon Laboratories Inc
文件页数: 6/12页
文件大小: 0K
描述: DEV KIT FOR F005/006/007
标准包装: 1
其它名称: 336-1017
C8051F00x/01x-DK
6.1. System Clock Sources
The C8051F005 device installed on the target board features a internal oscillator which is enabled as the system
clock source on reset. After reset, the internal oscillator operates at a frequency of 2 MHz (±2%) by default but may
be configured by software to operate at other frequencies. Therefore, in many applications an external oscillator is
not required. However, an external crystal may be installed on the target board for additional applications. The tar-
get board is designed to facilitate the installation of an external crystal at the pads marked Q1. Refer to the
C8051F005 datasheet for more information on configuring the system clock source. Following are a few part num-
bers of suitable crystals:
Freq (MHz)
Digikey P/N
ECS P/N
18.432
11.0592
X146-ND
X089-ND
ECS-184-20-1
ECS-110.5-20-1
(20 pF loading capacitance)
(20 pF loading capacitance)
6.2. Switches and LEDs
Two switches are provided on the target board. Switch SW1 is connected to the RESET pin of the C8051F005
device on the target board. Pressing SW1 puts the device into its hardware-reset state. The device will leave the
reset state after SW1 is released. Switch SW2 is connected to the device’s general purpose I/O (GPIO) pin through
headers. Pressing SW2 generates a logic low signal on the port pin. Remove the shorting block from the header to
disconnect SW2 from the port pins. The port pin signal is also routed to a pin on the J2 I/O connector. See Table 1
for the port pins and headers corresponding to each switch.
Two LEDs are also provided on the target board. The red LED labeled PWR is used to indicate a power connection
to the target board. The green LED labeled with a port pin name is connected to the device’s GPIO pin through a
header. Remove the shorting block from the header to disconnect the LED from the port pin. The port pin signal is
also routed to a pin on the J2 I/O connector. See Table 1 for the port pins and headers corresponding to each LED.
Table 1. Target Board I/O Descriptions
Description
SW1
SW2
Green LED
Red LED
I/O
Reset
P3.7
P1.6
PWR
Header
none
J1
J3
none
6.3. Target Board JTAG Interface (J4)
The JTAG connector (J4) provides access to the JTAG pins of the C8051F005. It is used to connect the Serial
Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming. Table 2
shows the JTAG pin definitions.
Table 2. JTAG Connector Pin Descriptions
6
Pin #
1
2, 3, 9
4
5
6
7
8, 10
Description
+3 VD (+3.3 VDC)
GND (Ground)
TCK
TMS
TDO
TDI
Not Connected
Rev. 0.6
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